Abstract: An apparatus comprising a decode frame store, a B frame store, a first anchor frame store, and a second anchor frame store. The decode frame store may be configured to decode one or more free frames and generate one or more B video images and one or more anchor video images. The B frame store may be configured to receive the one or more B video images from the decode frame store. The first anchor frame store may be configured to receive the one or more anchor video images from the decode frame store. The second anchor frame store may be configured to receive the one or more anchor video images from the first anchor frame store.

Abstract: A method and apparatus for multi-level encrypted encoding and decoding of digital signals, which includes utilizing only one type of encoder and one type of decoder. This can be either the same encoder and decoder used in throughout the process, or multiple, identical encoders and decoders. This allows the system to compensate for atmospheric degradation with higher bandwidth efficiency and a simplified receiver structure. The invention further identifies a 2j symbol generation technique that maps in disjoint regions of X-dimensional space, which allows different data bits to be eliminated from the decoding scheme and maximizes the number of independent data substreams that can be maintained.

Abstract: An air filtration system uses a liquid to remove impurities from the air. A specialized chamber allows the air and liquid to contact each other in close proximity, so that the liquid can pick up not only particulate matter, but fumes and toxic gasses as well. The air can be bubbled through the liquid, or the liquid can be introduced into the chamber as a gentle rain, a spray, a vapor, a waterfall, or any other configuration that allows active contact between the two mediums. The liquid can then be cleaned of contaminants, e.g., by centrifugal force, while the liquid is then reused.

Abstract: Embodiments of the invention include an electrical interconnection structure for connection to large electrical contacts. The electrical interconnection includes a semiconductor substrate having a conductive pad layer formed thereon. A dielectric layer having a plurality of elongate trenches is formed over the conductive pad layer such that the elongate trenches extend through the dielectric layer to the underlying conductive pad layer. Elongate conductive contacts are formed in the elongate trenches to establish electrical connections to the underlying conductive pad layer. The long axes of the elongate bar trenches can be arranged substantially parallel to the long axes of the slots formed in the copper pad. Alternatively, the long axes of the bar trenches can be arranged transversely to the long axes of the slots formed in the copper pad. In some embodiments, the conductive contacts are formed such that they establish electrical connection with sidewalls of the underlying conductive pad layer.

Abstract: A self-time circuit and method are presented for reducing the write cycle time in a semiconductor memory. A “dummy” memory cell having the same timing requirements as the functional cells, and associated write logic are added to the standard circuitry of the memory device. The dummy write cell receives the same control signals used to write data to the functional cells of the memory, and is configured to issue a completion signal when a write access is concluded, causing the write cycle to be terminated. The circuit and method permits write cycle time to be reduced to the lowest practical value, independently of the read cycle time. This potentially increases the overall operating speed of the memory device. The circuit and method disclosed herein are adaptable to the most common types of memory devices, such as SRAM, DRAM and CAM.

Abstract: A cache may comprise a memory and control logic. The memory may be configured for storing data buffered by the cache. The control logic may be configured controlling accesses to the memory. The control logic may comprise a pseudo-noise generator and a trigger device. The pseudo-noise generator may be configured for generating a pseudo-random number representing, for a miss access requiring allocation, which of a plurality of possible addresses in the memory to use for the allocation. The trigger device may be configured for controlling a cycle of the pseudo-noise generator to output the pseudo-random number therefrom.

Abstract: An equalization receiver responds to two differentially-related digital input signals occurring at a predetermined communication frequency. First and second input devices respond to the input signals and supply drive signals of a magnitude amplified relative to input signal by a factor related to the current conducted by the input devices. First and second current separate sources are connected to conduct current through the first and second input devices. An equalization circuit is connected between the first and second current sources. The equalization circuit has a frequency dependent impedance characteristic which exhibits a minimum impedance and a maximum coupling of the first and second current sources for the greatest current conductivity and the greatest amplification at the predetermined frequency.

Abstract: An amplifier circuit includes a first input device coupled to a first input node and controlling a first current, a second input device coupled to a second input node and controlling a second current, a current source device coupled to a bias node and controlling a summed current of the first and second currents, a current mirror circuit, a first feedback circuit, a second feedback circuit, and a capacitor. The current mirror circuit generates a load current by mirroring the first current so as to provide an output signal voltage to an output node couple to the second output node. The first feedback circuit supplies a mirrored first current to the bias node, and the second feedback circuit pulls a mirrored second current from the bias node. The capacitor is coupled to the bias node and provides the bias voltage to the current source device.

Abstract: A dual plasma process generates a microwave neutral plasma remote from a semiconductor wafer and a radio frequency (RF) ionized plasma adjacent to the wafer for simultaneous application to the wafer. A first gas flows through a microwave plasma generation area, without a second gas in the gas flow, to generate the neutral microwave plasma. The second gas is added to the gas flow downstream of the microwave plasma generation area prior to an RF plasma generation area.

Abstract: A pre-placement delay model for a logical function block of an integrated circuit design includes a fan-in count variable, a fan-out count variable and a delay variable. The fan-in count variable has a value indicative of a number of inputs to the logical function block. The fan-out count variable has a value indicative of the number of inputs of other logical function blocks that are driven by an output of the logical function block. The delay variable has a value that is a function of the binary logarithm of the fan-in count variable and the binary logarithm of the fan-out count variable.

Abstract: A tri-state sense amplifier is provided, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.

Abstract: A signal interpolator comprises a fractional interpolator and a numeric controlled oscillator. The numeric controlled oscillator may generate a control signal for controlling the fractional interpolator. The numeric controlled oscillator generally comprises a register, a modulo-M device, and an adder. The register may hold a count value, and the modulo-M device may apply a modulo-M function to the count value to generate the control signal therefrom. The adder may add an increment value to the modulo-M signal from the modulo-M device, to update the count value in the register.

Abstract: A method for decoding an encoded signal. The method generally comprises the steps of (A) generating a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics, (B) generating a plurality of second precision state metrics for a selected subset of the first precision state metrics in response to a plurality of second precision branch metrics, (C) replacing the selected subset of first precision state metrics with the second precision state metrics, and (D) storing the first precision state metrics and the second precision state metrics.

Abstract: A dual-damascene process for forming an integrated circuit structure is described. The process includes forming a trench in a dielectric substrate, and forming a via mask layer over the dielectric substrate and the trench. An aperture is formed in the via mask layer overlying the trench, thereby exposing a portion of the underlying dielectric substrate. The exposed portion of the dielectric substrate is subjected to an ion beam to damage the exposed dielectric material. The damaged portion of the dielectric substrate is then removed, such as by etching, thereby forming a via cavity below the trench in the dielectric substrate. Generally, the damaged portion of the dielectric substrate etches at a faster rate than do adjacent non-damaged regions. With a faster etch, there is practically no outward spreading of the via cavity as the etch proceeds downward through the dielectric substrate, thereby forming a via cavity wall that is very nearly vertical.

Abstract: A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

Abstract: An apparatus comprising a system configuration generator, a system builder and a simulation verification environment. The system configuration generator may be configured to generate a random system configuration file of a structurally variable and complex system. The system builder may be configured to build a system level netlist in response to the random system configuration file. The simulation verification environment may be configured to verify the structurally variable and complex system in response to the system level netlist. The simulation verification environment may be configured to provide automatic random verification of the system in response to the random system configuration file.

Abstract: A method is presented for self-test and self-repair of a semiconductor memory device. Prior to the self-repair stage, both redundant and regular memory portions are comprehensively tested, preferably using a checkerboard bit pattern. Faulty rows identified in each memory portion during testing are recorded. Known-bad rows in regular memory are then replaced by known-good redundant rows in the self-repair stage, and the resulting repaired memory is retested for verification. Compared to existing methods, the new method is believed to provide improved test coverage, making it both more effective in identifying non-repairable memory devices and less prone to fail repairable ones.

Abstract: A method of standardizing a fabrication process for an integrated circuit. The fabrication process includes a preceding thermal energy sensitive process and at least one set of selectable succeeding thermal energy delivery processes. An integrated circuit structure is formed using the preceding thermal energy sensitive process. The preceding thermal energy sensitive process is characterized based at least in part upon the greatest amount of thermal energy delivered to the integrated circuit by one of the set of selectable succeeding thermal energy delivery processes. Then as subsequent processes are selected and accomplished, if they do not deliver the greatest amount of thermal energy as anticipated by the preceding thermal energy sensitive process, an additional amount of thermal energy is added, so as to preferably equal the anticipated greatest amount of thermal energy. In this manner, the characterization of the preceding thermal energy sensitive process attains its desired parameters.

Abstract: A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.