Abstract: An integrated circuit package is provided that allows high density routing of signal lines. A substrate of the package may include an upper surface upon which a bonding finger resides, a lower surface upon which a solder ball resides, and a signal conductor plane on which a signal trace conductor resides a dielectrically spaced distance between the upper surface and the lower surface. A first via may extend perpendicularly from the upper surface, connecting the bonding finger to the first portion of the signal trace conductor. A second via may extend perpendicularly from the lower surface, connecting the solder ball to the second portion of the signal trace conductor. The routing of the vias and signal trace conductors may cause the signal lines to either fan into or away from the area of the integrated circuit package adapted to receive the integrated circuit.

Abstract: A method for storing data in a solid state device, comprising the steps of (A) retrieving data from a source device, (B) storing said data in a compressed format to said solid state device and (C) accessing and uncompressing portions of said data from said solid state device, wherein said portions represent data to be executed in response to an address.

Abstract: A method of control cell placement for an integrated circuit design includes the steps of receiving as input a description of a datapath structure for a hardmac; calculating a globally optimum placement with respect to connection length and delay for a group of control cells in the plurality of control cells; placing the plurality of control cells in at least one placement box; adding the placement of the plurality of control cells to an existing placement of a plurality of datapath cells in the description of the datapath structure to generate a globally optimum datapath structure for the plurality of control cells; and generating as output the globally optimum datapath structure.

Abstract: A process is disclosed for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface of the substrate and in the trenches, and/or a filler layer of dielectric material blanket deposited over the liner layer to fill the trenches, may not be uniform.

Abstract: An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.

Abstract: An apparatus generally having a threshold slicer, a state logic device and a converter. The threshold slicer may be configured to generate a (i) first signal having an initial state of a plurality of states in response to a preceding value and a present value from an input signal and (ii) a second signal having a plurality of levels in response to the preceding value and the present value. The state logic device may be configured to generate a third signal having a sequence of the plurality of states starting with the initial state in response to the first signal. The converter may be configured to generate an output signal having the plurality of levels in response to the plurality of states in the third signal.

Abstract: A method and apparatus are provided for recycling power in an integrated circuit. The integrated circuit includes a plurality of nets and a switched capacitor network. The plurality of nets includes a first logic net having a tendency to repetitively switch between logic high and low states during normal operation of the integrated circuit. The switched capacitor network includes a plurality of capacitors, which are selectively decoupled from the plurality of nets, selectively coupled to the first logic net in parallel with one another, and selectively coupled to at least one of the nets in series with one another.

Abstract: An electrically non conducting material disposed within one or more of the voids of a probe card between a substrate thereof and a tester interface to reinforce the substrate against flexing, bending, and warpage.

Abstract: A first-order digital PLL configured to accommodate a large frequency difference between a clock signal embedded in an incoming data stream received by a phase-locked loop and a local reference clock signal received by a phase-locked loop circuit. The PLL includes a data sampler which receives the incoming data stream, a frequency-locked loop (FLL) which receives the incoming data stream and is connected to the data sampler, and a frequency synthesizer which receives the local reference clock signal and is connected to the FLL. The FLL is provides a signal having a frequency which is substantially equal to the frequency of the local reference clock signal when no incoming data stream is received by the FLL, and provides a signal having a frequency which is substantially equal to the frequency of the incoming data stream when the FLL receives the incoming data stream.

Abstract: Provided is a method and apparatus for pseudo-random noise (PN) code sequence hopping by storing a base state of a PN code sequence generator that generates a PN code sequence and by identifying a number of states to advance the PN code sequence, the number being greater than one. A transformation function is then obtained based on the number of states to advance the PN code sequence. The PN code sequence is advanced by the identified number of states from the base state to obtain a new state, by utilizing the transformation function. Finally, the new state is loaded into the PN code sequence generator and the PN code sequence generator is enabled with the new state.

Abstract: A data structure contains sequence number metadata which identifies an input/output (I/O) operation such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and also contains revision number metadata which identifies a subsequent I/O operation such as a read modify write on only a fractional component of the entire user data. The sequence number and revision number metadata are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error to a portion of the stripe is detected by a difference in sequence numbers for all of the components of data. An error arising after an I/O operation is detected by a revision number which is different from the correct revision number.

Abstract: A circuit and method are disclosed herein for a crystal oscillator, wherein the Q of the resonant network is not reduced through the loading effects of the oscillator's resistive bias network. The oscillator is configured as an operational transconductance amplifier (OTA) coupled to the resonant network. The OTA creates a negative resistance, which compensates for energy lost to resistance within the resonant network, thereby sustaining oscillation at the resonant frequency. Instead of using bias resistors to set and maintain the operating point of the oscillator, another OTA (with a high output impedance) injects a current into the resonant network to bias the oscillator. Advantageously, this technique avoids the reduction in Q that occurs when bias resistors are connected across the high effective parallel resistance of the resonant crystal. The higher Q benefits frequency stability and phase jitter characteristics of the oscillator.

Abstract: A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer.

Abstract: Interconnectors are placed on a die containing a semiconductor device or integrated circuit which is to be tested or analyzed. The interconnector includes a bump contact for contacting a bond pad of the die, and a probe pad at a position spaced from the bump contact. An interconnector connects the bump contact and the probe pad. The interconnector is attached to the die with the bump contact in electrical contact with the bond pad and with the probe pad extending beyond an exterior peripheral edge of the die. Probes apply signals or power to the probe pad, and those signals and power are applied to the semiconductor device or integrated circuit to establish functionality for the test or analysis.

Abstract: A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon germanium channel layer on the substrate. A gate insulation layer is formed on top of the strained silicon germanium channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source-drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal.

Abstract: An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.

Abstract: An integrated circuit package includes a connector board and plural levels of individual conductors and conductive vias disposed through the connector board to form electrical connections between external connection pads on an undersurface of the connector board and finger connections on the upper surface of the connector board. An integrated circuit die is mounted in a central region of the connector board within confines of the individual conductors that are arranged about the die, and wire bond connections are formed between selected ones of the finger connections, the individual conductors, and the connection pads on the integrated circuit die to provide distributed connections for ground and power at one or more operating voltage levels on the individual conductors.

Abstract: A method and circuit control a quiescent current of an amplifier including a preamplifier, error amplifiers, and output devices driven by the error amplifiers, the error amplifiers having an input-referred offset voltage. The method includes (a) applying a calibration voltage to an input of the error amplifiers, (b) calibrating a quiescent current of the output devices by changing the calibration voltage so that the calibrated quiescent current has a predetermined current value, the calibration voltage corresponding to the calibrated quiescent current being set as a correction voltage, and (c) operating the amplifier with the correction voltage applied to the input of the error amplifiers. The circuit includes a correction voltage generator supplying a correction voltage to the error amplifier input, a quiescent current detector detecting the quiescent current, and a calibration circuit adjusting the correction voltage so that the quiescent current is calibrated to a predetermined current value.

Abstract: A read data synchronization circuit for use in a Double Data Rate (DDR) memory system is provided. The read data synchronization circuit provides programmable timing signals for use in synchronizing read data.

Abstract: A package substrate having sides, which is formed of multiple non electrically conductive layers laminated together. Each of the multiple non electrically conductive layers is formed of a first lamina and a second lamina bonded together in a resin matrix. The first lamina is formed of woven fibers having a first warp. The first warp of the first lamina is disposed at a positive orientation of a first angle from the sides of the package substrate, where the first angle is neither zero degrees nor ninety degrees. The second lamina is also formed of woven fibers, having a second warp. The second warp of the second lamina is disposed at a negative orientation of the first angle from the sides of the package substrate. Electrically conductive layers are dispersed between different ones of the multiple non electrically conductive layers, with electrical connections dispersed between different ones of the electrically conductive layers.