Abstract: The present invention is directed to platform architecture. A system for providing distributed dynamic functionality in an electronic environment may include a plurality of platforms. The platforms are suitable for providing a logic function, and include embedded programmable logic, memory and a reconfigurable core. The logic, memory and reconfigurable core are communicatively coupled via a fabric interconnect. A map is also included which expresses logic functions of the plurality of platforms.

Abstract: Dummy wafers that are used in IC manufacturing and methods for manufacturing the same are described. The dummy wafers are made with an increased resistance to breaking during CVD manufacturing process. The dummy wafers are made by placing a protective film over the wafer surface(s) exposed during the CVD process. By increasing the resistance to breaking, the protective film extends the useful life of the dummy wafers.

Abstract: A method of receiving a plurality of instructions. The method generally comprises the steps of (A) storing a first of the instructions in response to receiving the first instruction at an initial time, and (B) rejecting a second of the instructions that depends from the first instruction in response to receiving the second instruction greater than a maximum delay after the initial time.

Abstract: Accordingly, the present invention is directed to a method of managing data in a storage system. A method of performing a write to data storage system, including a first storage device and a second storage device, may include writing a first set of header information to a first storage device and a second storage device. The first set of header information includes a first sequence number and a second sequence number, in which the first set of header information includes a first sequence number incremented to indicate a change from the second sequence number. Data is written to the first storage device and the second storage device. Then, a second set of header information is written to a first storage device and a second storage device. The second set of header information includes a first sequence number and a second sequence number, in which the second set of header information includes a second sequence number incremented to correspond to the first sequence number.

Abstract: A phase error measurement circuit for measuring phase error between two clocks on an integrated circuit is provided. The measurement circuit includes first and second clock signal inputs, a phase lead detector, a phase lag detector and a phase error measurement output. The phase lead detector includes a phase lead latch having a data input, which is coupled to the first clock signal input, a latch control input, which is coupled to the second clock signal input and a data output. The phase lag detector includes a phase lag latch having a data input, which is coupled to the second clock signal input, a latch control input, which is coupled to the first clock signal input and a data output. The phase error measurement output is formed by the data outputs of the phase lead latch and the phase lag latch.

Abstract: The present invention is a method for searching an identity base for identities that can be applied to a given formula. The method includes transforming the formulas from an identity base into a standard form, creating a set of code words for said identity base, constructing a lexicographical tree of a code word set of said identity base, and outputting a list of formula numbers from said identity base.

Abstract: Provided is a method and an apparatus for pseudo-random noise (PN) code sequence hopping, in which an output PN code sequence is generated by generating and combining several intermediate PN code sequences, each of the intermediate PN code sequences being generated by a corresponding PN code sequence generator. A base state is stored for each of the plural intermediate PN code sequences, and the number of states to advance the output PN code sequence is identified, the number being greater than one. A transformation function is obtained for each of the plural intermediate PN code sequences, based on the number of states to advance the output PN code sequence, and then the base state for each intermediate PN code sequence is advanced by the number of states to advance the output PN code sequence, by utilizing the transformation function for such intermediate PN code sequence, to obtain a new state for such intermediate PN code sequence.

Abstract: A method for selectively placing cells of an application-specific integrated circuit on a substrate surface, including the steps of defining a grid covering a substrate surface, assigning cells to the grid to provide old x and y coordinates of the cells relative to the grid, grouping the cells by function to provide functional regions within the grid, determining a density map of the surface of the substrate in all the functional regions within the grid, determining free space of the grid on the surface of the substrate relative to the density map, and assigning new cells to the free space of the grid on the substrate surface to provide an application specific integrated circuit. Use of the method provides improved layout of an integrated circuit with minimal cell congestion or overlapping.

Abstract: An apparatus for reducing residual oxygen content from a processing chamber of an atmospheric reactor after the processing chamber of the atmospheric reactor has been exposed to an oxygen environment. The processing chamber of the atmospheric reactor has an inert gas purge, including an inert gas source, for reducing a residual oxygen level within the processing chamber of the atmospheric reactor at a rate of reduction. A venturi vacuum system is enabled by the inert gas source. The venturi vacuum system draws a vacuum on the processing chamber of the atmospheric reactor and supplements the inert gas purge, thereby accelerating the rate at which the residual oxygen level is reduced within the processing chamber of the atmospheric reactor. In this manner, the vacuum created by the venturi vacuum system increases the efficiency of the inert gas purge by reducing by some moderate degree the pressure within the processing chamber of the atmospheric reactor.

Abstract: A method for data verification in a data storage environment comprising the steps of (A) sending a command from an initiator to a target, where the command defines an expected data pattern, (B) sending a block write command from the initiator to the target, where the write command initiates sending data from the initiator to the target, (C) comparing data received to the expected data pattern and (D) generating a status indication in response to the comparison.

Abstract: An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation. The BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution during the BIST and BISR operations. The memory blocks may be remapped in response to the count values during one or more of the BISR operations.

Abstract: A method and system for correcting quantization loss of a signal during analog to digital to analog signal conversion, wherein the quantization loss is a function of (sin x)/x, is disclosed. The system and method of the present invention includes utilizing a continuous function polynomial to represent a (sin x)/x function, and applying an inverse function of the continuous function polynomial to the signal to provide a correction for the quantization loss.

Abstract: A bus bridge generally comprising a first interface, a second interface, a plurality of registers and a controller. The first interface may be connectable to a first bus having a first data width. The second interface may be connectable to a second bus having a second data width narrower than the first data width. The plurality of registers may be configured to buffer (i) data, (ii) an address, and (iii) a plurality of control signals between the first bus and the second bus. The controller configured to control the registers.

Abstract: An improved PCI-X verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI-X system. One or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values. In one aspect, an apparatus and method for testing a PCI-X device for compliance under the PCI-X Addendum to the PCI Local Bus Specification in completer operation are provided. In another aspect, an apparatus and method for testing a PCI-X-device for compliance under the PCI-X addendum to the PCI Local Bus Specification in requester operation are provided.

Abstract: An apparatus and method for translating variable-length instructions to fixed-length instructions. The apparatus includes instruction decompression logic and caching logic. The instruction decompression logic receives a first portion of an instruction data block, an output signal produced by the caching logic, and a control signal during a time period. The instruction decompression logic produces a fixed-length instruction during the time period dependent upon the first portion of the instruction data block, the output signal produced by the caching logic, and the control signal. The caching logic includes a storage unit. During the time period, the caching logic receives a second portion of the instruction data block and the control signal. The caching logic stores the second portion of the instruction data block within the storage unit during the time period dependent upon the control signal.

Abstract: A system for disabling defective memory elements includes a memory array, an address decoder and a decoder element. The memory array has multiple memory elements for storing data. The address decoder receives a requested memory address and produces multiple element-select signals. Each element-select signal is associated with one of the memory elements and indicates whether access to the associated memory element is requested by the host. The decoder element receives one of the element-select signals and provides an output signal to the associated memory element. If the associated memory element is functional, the output signal enables or disables the associated memory element in accordance with the associated element-select signal. If, on the other hand, the associated memory element is defective, the output signal disables the associated memory element regardless of the associated element-select signal.

Abstract: Delay and/or load estimation is performed prior to physical layout in an integrated circuit (IC) design process. Initially, a description of the IC design is obtained, the description being in a hardware description language (HDL). Floor planning is then performed based on the HDL description, and buffers are inserted into the IC design based on such floor planning. Finally, delays and/or loads are estimated in the IC design while taking into account the effect of the buffers. The buffers are inserted in the foregoing processing based on anticipated processing later in the IC design process.

Abstract: A circuit for synchronizing an internal time signal to an external time signal includes a first timer, a second timer, and a comparator. The first timer repetitively increments and outputs a first time signal. The second timer repetitively outputs a second time signal. The comparator drives an active comparator signal if the first time signal is greater than the second time signal, or otherwise an inactive signal. The first timer saves the second time signal as the first time signal in response to a control signal derived from the inactive comparator signal and repetitively increments and outputs the first time signal. Alternatively, the first timer freezes, i.e., preventing the repetitive incrementing, of the first time signal in response to a control signal derived from the active comparator signal. The second timer repetitively increments and outputs the second time signal in response to a control signal derived from the active comparator signal.

Abstract: A technique for detection and bypass of unnecessary modulation/demodulation and compression/decompression of Group 3 fax, in a telecommunication network having more than one pair, or “tandem,” Group 3 fax relay gateways. Detection and the effective removal of a Group 3 fax tandem reduces end-to-end processing delays of the facsimile signal, and improves performance of the Group 3 fax communication. The invention uses frequencies normally used for voice information (such as V.21 channel 1 frequencies) to detect tandem fax relay gateways and effectively remove unnecessary relay gateways.

Abstract: A system, apparatus and/or method is provided for removing water vapor from a wafer processing chamber generated as a byproduct of wafer processing. A water vapor trap is used to collect the water vapor byproduct from the processing chamber interior. The water vapor trap has at least a portion thereof in communication with an interior of the processing chamber for collection of the water vapor and another portion thereof in communication with an exterior of the processing chamber. The portions are movable with respect to the interior and exterior of the processing chamber such that the portions may switch places. This allows the processing chamber to be in at least a substantially continuous mode of operation while still providing for the removal of water vapor byproduct via the water vapor trap. The “used” portion of the water vapor trap is regenerated while the “clean” portion is collecting water vapor.