Abstract: An apparatus comprising a first calibration circuit and a phase shift network stage. The first calibration circuit may be configured to generate a control signal. The phase shift network stage may comprise one or more tunable phase shift elements and be configured to provide a tunable impedance. The phase shift network stage may be tuned in response to the control signal and a conductance of the tunable phase shift elements.

Abstract: The present invention describes a multi-stage decoder and method of decoding utilizing a pseudo NAND or pseudo AND gate in one of the stages. This invention presents a decoder comprising a first stage circuit having two or more first inputs which generates one or more first outputs; and a second stage circuit having at least one second input and at least one second output, wherein the one or more first outputs are the same as the at least one second input, wherein at least one of the group consisting of the first stage circuit and the second stage circuit includes either a pseudo AND gate or a pseudo NAND gate. This invention presents a method of decoding, comprising the steps of generating a signal responsive to two or more address bits and enabling a decoder by the generated signal.

Abstract: A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material.

Abstract: An improved PCI verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI system. One or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values. In one aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in target operation is provided. In another aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in master operation is provided.

Abstract: A high Q tank circuit is employed at the output of a digital, crystal controlled oscillator to generate a high voltage amplitude signal. The tank circuit has a resonant frequency greater than the maximum required oscillation frequency. During each oscillation cycle, oscillation within the tank circuit is stopped in an energy efficient manner such that the resonant oscillation period is extended to match the required oscillation period. Modulation of the digital oscillator signal appears in the output circuit signal.

Abstract: A process for forming a low k carbon-doped silicon oxide dielectric material (lkc-dsodm) on an integrated circuit structure is characterized by improved planarity and good gap fill in high aspect ratio regions of the integrated circuit structure, as well as improved film strength and adherence, and less byproducts trapped in the film. The process comprises: depositing a plurality of layers of lkc-dsodm on an integrated circuit structure in a reactor; and pausing after depositing each layer of lkc-dsodm and before depositing a further layer of lkc-dsodm. The process can further include first forming a base or barrier layer of a silicon-rich and nitrogen-rich dielectric material over the integrated circuit structure, plasma etching the upper surface of the barrier layer to facilitate adhesion of the subsequently deposited lkc-dsodm to the barrier layer, and then, before depositing the first layer of lkc-dsodm, cooling the etched barrier layer down to within 10° C.

Abstract: An adaptive equalizer for use in a communication receiver that prevents equalizer operation divergence in response to slicer errors in a high noise communication application. The equalizer uses the difference between an equalized sample value and the nearest constellation point determined by the slicer both as the equalizer adaptation value and as a control value to selectively enable or minimize (disable) adaptation modifications. The difference is compared to a threshold value to determine whether the difference should be applied to the equalizer for adaptation purposes or a minimal value to prevent equalizer divergence in response to significant slicer errors. The threshold value is determined as a function of the ratio of the probability of correct slicer determinations and the probability of incorrect slicer determinations for a given sample value and a given signal to noise ratio.

Abstract: The present invention concerns an apparatus comprising a fixture and a sputtering device. The fixture may be configured to position a semiconductor wafer in a plasma. The sputtering device may be configured to sputter metal atoms onto a surface of the wafer in a direction perpendicular to the surface.

Abstract: A method of configuring a plurality of managed devices. The method preferably includes selecting a source managed device, obtaining a source configuration description from the source managed device, selecting one or more destination managed devices to be configured, issuing a configuration change command to each of the selected destination managed devices and applying the source configuration description selected from the source managed device to each of the selected destination managed devices. In addition, the method may further include the step of editing the source configuration description before issuing the configuration change commands to the one or more destination managed devices.

Abstract: A circuit that may comprise a data-cache memory and a data-path circuit. The data-cache memory may be configured to (i) store a cache input data item among a plurality of associative sets and (ii) present a plurality of cache output data items. The data-path circuit may be configured to (i) independently shift each of the plurality of cache output data items and (ii) multiplex the plurality of shifted cache output data items to present an output data item.

Abstract: A system and method for dynamically expanding a snapshot repository based on predefined parameters is disclosed. The snapshot repository is monitored for determining if the amount of information stored in the snapshot repository has reached a predetermined volume increase threshold. If a determination is made that the volume increase threshold has been reached, the volume of the snapshot repository is automatically increased. The snapshot repository may also be monitored for determining if the amount of information stored in the snapshot repository has reached a predetermined maximum snapshot repository volume whereupon a warning may be provided.

Abstract: A method and apparatus for arbitrating access to a memory, which has a plurality of banks. The method includes arbitrating with a plurality of processors. Each processor is associated with one of a plurality of data ports and has a plurality of arbitration cycles, including a current cycle and a most recent cycle preceding the current cycle. Each processor receives memory access requests from all of the data ports, wherein each memory access request is associated with one of the memory banks. Each processor selectively grants the data port associated with that processor access to the memory for the current cycle based on the banks associated with the memory access requests of each data port, the data port that was granted access to the memory during the preceding cycle, and the memory bank that was accessed during the preceding cycle.

Abstract: A method for simulating verification of an IC design. The method generally comprises the steps of (A) generating one or more transactions of a simulation and (B) testing the one or more transactions and possibly generating an exception. The exception may be configured to initiate a modification of step (A).

Abstract: A method of applying a layer of material to a substrate. The substrate is received with a chuck, and the material is dispensed. The substrate is spun on the chuck, spreading the material and conveying a surplus of the material away. The surplus of the material conveyed away is entrained into an exhaust stream. A pressure drop is created in the exhaust stream across a vane anemometer. The blow back of the entrained surplus of the material from a downstream position in the exhaust system to the substrate is thereby reduced.

Abstract: A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10° and about 75° as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.

Abstract: A platen for use in a dry etching process for substrate production, the platen having a surface susceptible to chipping and/or particle generation from the dry etching process and a coating applied to at least a portion of the surface for rendering the surface less susceptible to chipping and/or particle generation, the coating comprising a silicon carbide coating

Abstract: A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels.

Abstract: A system which simplifies the clock tuning process for a clock buffer tree. Essentially, a clock buffer tree is provided where the clock buffer tree includes clock buffers of different strengths. The different strength clock buffers which are in the clock buffer tree have the same pin-out configuration. Hence, it is easy and straightforward to upsize or downsize any of the clock buffers in the clock buffer tree, and it is guaranteed that the new cell will fit into the old cell's slot in the tree. Since none of the nets need to be modified, consistent timing results are achieved. Moreover, the new timing for the modified clock buffer can be anticipated because its wire loading does not change at all. The ease of clock tuning makes it much easier to design clock buffer trees and layouts, and allows the overall design to be completed faster and easier.

Abstract: A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.

Abstract: A reaction chamber of the type used to create a reaction at a surface of a substrate disposed within the reaction chamber. A transmitter produces a transmitted beam having first characteristics, where the transmitter is disposed outside of the reaction chamber. A view port is disposed in a boundary wall of the reaction chamber, where the view port is formed of a material that is transparent at least in part to the transmitted beam. The transmitter, the view port, and the substrate are aligned such that the transmitted beam is directable to and reflected at least in part from the surface of the substrate, thereby producing a reflected beam having second characteristics. A receiver is disposed outside of the reaction chamber, and the receiver receives the reflected beam from the surface of the substrate through the view port. The receiver also senses the second characteristics of the reflected beam and reports the second characteristics.