Abstract: A method and apparatus for a propagation delay and time calibration. The apparatus includes a ring oscillator having a first set of elements. The apparatus also includes delay units. The ring oscillator is used to generate a clock signal used to measure the delay in signals received at the delay blocks. In the depicted examples, the clock signal generated by the ring oscillator is used to run a counter that counts the delay between a transition in a data signal and a reference signal. Each of the delay units includes a second set of elements matching those of the first set of elements in the ring oscillator. The elements in the set of elements are selected such that they track the period of the ring oscillator signal generated by the ring oscillator. The delay units are used to implement the desired delay.

Abstract: A process is herein described for analyzing an integrated circuit chip for defects by observing changes in the appearance of a liquid crystal applied to the backside of the integrated circuit. The process includes spreading a thin film of a liquid crystal material on the backside of the integrated circuit. Using an optical microscope, the liquid crystal film is optically inspected as the chip is biased.

Abstract: A method of datapath cell placement is disclosed that minimizes signal propagation time through a datapath macro and datapath macro area that includes the steps of receiving as input a datapath description for a datapath block wherein the datapath description describes at least one of a plurality of datapath cells, a plurality of data input pins, a plurality of data output pins, and a plurality of control signal pins; sorting the plurality of data input pins and the plurality of data output pins according to a hierarchy of sorting criteria; determining a plurality of corresponding criticality values for the plurality of datapath cells; sorting the plurality of datapath cells according to the plurality of corresponding criticality values; assigning the plurality of datapath cells to a plurality of corresponding columns; and arranging the plurality of datapath cells within at least one of the plurality of corresponding columns to minimize signal propagation delay through the datapath block.

Abstract: A drum washer has a base, a barrel support structure, and a water delivery system. A hollow drum is turned over and placed on the drum washer by inserting a spray head of the water delivery system through a hole in a top cover of the drum and into the interior of the drum. The barrel support structure holds the drum at a fixed angle while water is sprayed from the spray head onto interior surfaces of the drum. The water rinses the interior surfaces of the drum and drains out the hole in the top cover of the drum.

Abstract: An apparatus comprising a control circuit and a logic circuit. The control circuit may be configured to receive an input signal and an indication signal and present a complement of the input signal. The logic circuit may be configured to receive the complementary input signal and generate an output signal. The output signal may provide full scale voltages between a first supply (e.g., VSS) and a second supply (e.g., VDD2).

Abstract: Via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped sidewall. Such a sloped sidewall via can be etched in a low k dielectric layer by first forming a via resist mask over the upper surface of such a dielectric layer, then heat treating the mask sufficiently to deform the sidewall geometry of the resist mask to form a sloped sidewall on the opening or openings in the heat treated resist mask. The resulting erosion of such a resist mask, during a subsequent etch step to form the via in the low k dielectric material through such a sloped sidewall resist mask, imparts a tapered or sloped sidewall geometry to the via which is then formed in the underlying layer of low k dielectric material.

Abstract: Provided is a vertically integrated (“chip-over-chip”) semiconductor package and packaging method. The invention provides higher packaging density and performance, including increased functionality, decreased signal propagation delays, improved circuit switching speed, lower thermal resistance and higher thermal dissipation measurements, relative to previous package designs. According to the invention, a semiconductor package may be composed of a flip chip (or chips) overlying one or more other flip chips, all electrically bonded to flip chip bond pads on a cavity-less semiconductor substrate. The upper and lower flips chips may be assembled in a variety of different configurations and may be thermally or electrically connected to each other. In a preferred embodiment, the flip chips, particularly the lower flip chip(s), are thinned so that the overall package height is within conventional ranges for traditional single chip packages.

Abstract: An arrangement for polishing a semiconductor wafer is disclosed. The arrangement includes a plurality of preassembled polishing pad assemblies which can be selectively coupled to, and decoupled from, an actuating mechanism for rotating the polishing pad assemblies. An associated method of polishing a semiconductor wafer is also disclosed.

Abstract: An on-chip built-in self test apparatus for a phase locked loop module that resides on an integrated circuit, receives a reference clock signal and provides an output clock signal. The apparatus generally comprises a finite state machine and testing circuitry. The finite state machine may be for (i) receiving the reference clock signal and for (ii) producing testing signals for the phase locked loop module. The testing circuitry may be coupled to the finite state machine for (i) receiving the output clock signal, (ii) determining whether the characteristics of the output clock signal meet a predetermined criteria for open and close loop phase locked loop module operation, and (iii) outputting a test signal that indicates proper phase locked loop module operation if the characteristics of the output clock signal meet the predetermined criteria.

Abstract: A communications receiver includes an analog input for receiving an analog signal having a time-varying DC voltage drift. A variable gain amplifier is coupled to the analog input and is adapted to amplify the analog signal based on a gain set by a gain control input to the amplifier. An analog-to-digital (A/D) converter is coupled to an output of the amplifier and is adapted to convert the amplified analog signal to a series of digital values. A drift estimator is coupled to the A/D converter, which generates an estimate of the time-varying DC voltage drift based on the series of digital values. A gain adjuster is coupled between the drift estimator and the amplifier, which adjusts the gain control input based on the drift estimate.

Abstract: A method of testing semiconductor devices on a wafer, including a tasting circuit formed on the wafer for providing an output signal indicative of at least one operational characteristic of the devices. The output signal provided by the testing circuit is compatible for monitoring using an integrated circuit tester. The testing circuit includes an oscillator, an N-bit counter, and an N-bit shift register, all formed on the semiconductor wafer. The tester resets the counter and enables the oscillator, at which time the oscillator produces oscillator pulses at an oscillator frequency. During a predetermined time period, the counter receives and counts the oscillator pulses from the oscillator, and produces a pulse count corresponding to the number of oscillator pulses received. The shift register receives the count from the counter as an N-bit digital data word. The tester shifts the N number of bits of the digital data word out of the shift register, and manipulates the bits to determine a count value.

Abstract: A computer program that improves a netlist of logic nodes and physical placement for an IC. The program (a) identifies critical nodes based on delay information calculated from the physical placement. Then the program (b) selects a set of critical nodes and optimally collapses their critical fan-ins and part of the non-critical fan-ins based on their Boolean relationship, which, includes at least one critical node. After that, the program (c) remaps the collapsed sub-netlist by covering its subject graph with an optimal pattern graph, and dynamically estimates and updates the fanout loads. The program returns to step (b) if the remapped sub-netlist is unacceptable, and returns to step (a) after updating the delay information and coordinates of newly mapped gates if the remapped sub-netlist is acceptable. The program exits at step (a) when no more critical nodes are identified at step (a).

Abstract: A transportable memory apparatus including cache memory and a backup battery is provided that is capable of being removed from a first computer system and installed within a second computer system. The transportable memory apparatus includes a control bus that provides appropriate signals such that the presence and status of the transportable memory apparatus can be detected in order to permit the computer system that includes the transportable memory apparatus to be appropriately initialized. As such, methods for initializing a computer system that may include a transportable memory apparatus are also provided.

Abstract: The inter-symbol interference problem is reduced by detecting a data sequence indicating when a boost is needed on a ‘short pulse’, usually the first data pulse of the opposite polarity after a string of data pulses of the same value. A data decoder that detects when current compensation is required and an output driver that has the variable drive capability to change the drive current on the short pulse is used to boost the amplitude. The output driver is regulated by a phase locked loop which includes a voltage variable delay digitally controlled voltage variable reference capacitors in the phase locked loop circuit for receiving data from memory that contains the proper capacitor control voltage needed. The time required to charge the capacitor is constant and the delay is slaved to the clock period.

Abstract: An enclosure module for accommodating a plurality of peripheral devices having: a computerized control unit in electrical communication with a user interface, a first and second bus with a bus expansion logic element therebetween that allows for operation of the buses as a single logical bus or as independent buses, termination circuitry for signal-appropriate bus termination, and a first and second plurality of connectors, each for electrical connection with one of the peripheral devices. The user interface to accept a first input (and can include a second, third, fourth, and so on, input) for optional manual configuration of a respective operational feature of the enclosure module, and if the input(s) is not registered, the feature can be automatically configured without the particular information provided by the input. The connectors can each have a multi-connect assembly for connection with a first, second, and third type connector.

Abstract: A method of forming a via in a circuit, such that parasitic capacitance is reduced. The surface layers of the circuit are identified, to which continuity with the via is desired, and secondary layers of the circuit are also identified. Via lands are formed only on the surface layers and not on the secondary layers. The via lands are formed in first portions of the surface layers, where the via is to pass through the surface layers. Nonconductive cut outs are formed in second portions of the secondary layers where the via is to pass through the secondary layers. The surface layers and the secondary layers of the circuit are laminated together. The first portions of the surface layers are aligned with the second portions of the secondary layers. A through hole is formed through the via lands formed in the surface layers, and also through the cut outs formed in the secondary layers. The via is formed in the through hole.

Abstract: Sequence number metadata which identifies an input/output (I/O) operation, such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and revision number metadata which identifies an I/O operation such as a read modify write operation on user data recorded in components of the stripe, are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error arising after a full stripe write is detected by a difference in sequence numbers for all of the components of user data in the stripe. An error arising after a read modify write is detected by a revision number which occurred before the correct revision number.

Abstract: A switched gain differential amplifier is provided which includes first and second differential transconductance amplifier stages and a disabled dummy differential transconductance amplifier stage. The first and second differential transconductance amplifier stages have respective differential inputs that are coupled in-phase to one another and respective differential outputs that are coupled in-phase to one another. At least one of the stages is selectively enabled. The disabled dummy differential transconductance amplifier stage has a differential input coupled in-phase to the differential inputs of the first and second differential transconductance amplifier stages and a differential output cross-coupled out-of-phase to the differential outputs of the first and second differential transconductance amplifier stages.

Abstract: A clock gating cell and a method of manufacturing the same. In one embodiment, the clock gating cell includes: (1) gate signal and clock signal inputs configured to receive gate enable and clock input signals, respectively, and (2) a gated clock signal output configured to generate a gated clock signal that is a function of states of the gate enable and clock signals, the clock gating cell treated as an atomic entity in a cell library.

Abstract: A binary search tree is structured so that keys or addresses associated with data in the bottom vertices are arranged in a predetermined order, such as ascending key address order. The root vertex and each hierarchy vertex contains the lowest value key from each child vertex and are thus similarly arranged by key value order. Each vertex of each level contains at least k and no more than 2k−1 keys, where k is an integer ≦2 and is constant for all vertices of a given level, but may vary between levels. The result is a structured tree having equal path lengths between the root vertex and each bottom vertex for search purposes. Keys are deleted and inserted to the bottom vertices by restructuring the tree under control of computer instructions.