Abstract: Embodiments of the invention include a capping layer of alloy material formed over a copper-containing layer, the alloy configured to prevent diffusion of copper through the capping layer. In another embodiment the alloy capping layer is self-aligned to the underlying conducting layer. Specific embodiments include capping layers formed of alloys of copper with materials including but not limited to calcium, strontium, barium, and other alkaline earth metals, as well as materials from other groups, for example, cadmium or selenium. The invention also includes methods for forming an alloy capping layer on a copper-containing conducting structure. One such method includes providing a substrate having formed thereon electrically conducting layer comprised of a copper-containing material and forming an alloy capping layer on the electrically conducting layer. In another method embodiment, forming the alloy capping layer includes forming a self-aligned capping layer over the conducting layer.

Abstract: A transportable memory apparatus including cache memory and a backup battery is provided that is capable of being removed from a first computer system and installed within a second computer system. The transportable memory apparatus includes a control bus that provides appropriate signals such that the presence and status of the transportable memory apparatus can be detected in order to permit the computer system that includes the transportable memory apparatus to be appropriately initialized. As such, methods for initializing a computer system that may include a transportable memory apparatus are also provided.

Abstract: An apparatus and method for filtering glitches in data signals are provided. The apparatus and method provide a programmable glitch filter that may be programmed to filter glitches of different depths. The apparatus and method further provide a glitch filter that is programmable and incorporates a synchronizer for synchronizing the filtered output from the glitch filter to a different clock domain than that of the clock input.

Abstract: A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric material from silicon, nitrogen and hydrogen allows a stoichiometric ratio control of silicon to nitrogen to limit the amount of hydrogen. Forming the capacitor by dielectric material plasma enhanced chemical vapor deposition (PECVD) allows hydrogen bonds to be broken by ionic bombardment, so that stoichiometric control is achieved by controlling the power of the PECVD. Applying a predetermined number of thermal cycles of temperature elevation and temperature reduction also breaks the hydrogen bonds to control the amount of the hydrogen in the formed capacitor dielectric material.

Abstract: A method of planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom is described. The method includes the step of positioning a fluid flow surface relative to the wafer surface so that (i) a space is defined between the wafer surface and the fluid flow surface, and (ii) the elevated portion of the semiconductor wafer is positioned in the space. The method also includes the step of advancing a fluid within the space so that the fluid contacts and erodes the elevated portion of the semiconductor wafer. An associated apparatus for planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom is also described.

Abstract: A circuit generally comprising a first circuit and a phase lock loop. The first circuit may be configured to (i) collect a plurality of samples per cycle during a plurality of cycles of an input signal and (ii) calculate a phase offset and a frequency offset for the input signal relative to a clock signal in response to the samples. The phase lock loop may be configured to (i) preset a phase error signal to the phase offset and a frequency error signal to the frequency offset and (ii) generate the clock signal in response to the phase error signal and the frequency error signal.

Abstract: A portion of a storage controller's cache memory is used as a virtual solid state disk storage device to improve overall storage subsystem performance. In a first embodiment, the virtual solid state disk storage device is a single virtual disk drive for storing controller based information. In the first embodiment, the virtual solid state disk is reserved for use by the controller. In a second embodiment, a hybrid virtual LUN is configured as one or more virtual solid state disks in conjunction with one or more physical disks and managed using RAID levels 1-6. Since the hybrid virtual LUN is in the cache memory of the controller, data access times are reduced and throughput is increased by reduction of the RAID write penalty. The hybrid virtual LUN provides write performance that is typical of RAID 0. In a third embodiment, a high-speed virtual LUN is configured as a plurality of virtual solid state disks and managed as an entire virtual RAID LUN.

Abstract: The present invention comprises method for optimizing an integrated circuit design that includes computing of capacities and delays of an integrated circuit design, resynthesizing said integrated circuit design utilizing a plurality of local optimization procedures, and removing overlap the local optimization procedures can include a local resynthesis of logic trees procedure that utilizes multiple cost functions, a dynamic buffer and inverter tree optimization procedure, and a cell resizing procedure. Generally, faster local optimization procedures are applied first and slower, more thorough procedures are applied to areas where the faster procedures have not solved the optimization tasks.

Abstract: Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer.

Abstract: Control of a reaction between a peroxide oxidizing agent and a carbon-substituted silane to form a low k carbon-containing silicon oxide dielectric material is achieved, in a first embodiment, by adding, to the carbon-substituted silane reactant, silane (SiH4), to accelerate the process for forming a low k carbon-containing silicon oxide dielectric material by reaction of the carbon-substituted silane/silane mixture with hydrogen peroxide. Also, control of a reaction between a peroxide oxidizing agent and a carbon-substituted silane to form a low k carbon-containing silicon oxide dielectric material is achieved by controlling the ratio of the flow of the hydrogen peroxide reactant and the flow of the reactant mixture of carbon-substituted silane and unsubstituted silane into the reaction chamber though structural modification of the faceplate (showerhead) through which the reactants flow into the chamber.

Abstract: A subprefix is selected from a prefix search tree that has a longest match to a search prefix. A binary search prefix is input to the root vertex of the tree, and is compared to the prefixes in selected hierarchy vertices. A bit is set in a search mask based on a least significant bit of a bit string in the search prefix that matches a longest bit string in a prefix in each vertex. A longest matching subprefix is selected from a string of most significant bits of the search prefix based on the lowest significant bit set in the search mask. A prefix mask is also provided for each prefix in the tree, and is useful in connection with construction of the search mask.

Abstract: A process is disclosed for removing a photoresist mask used to form openings in an underlying layer of low k carbon-doped silicon oxide dielectric material of an integrated circuit structure formed on a semiconductor substrate, which comprises exposing the photoresist mask in a plasma reactor to a plasma formed using a reducing gas until the photoresist mask is removed. In a preferred embodiment the reducing gas is selected from the group consisting of NH3, H2, forming gas, and a mixture of NH3 and H2.

Abstract: A system and method are disclosed for equalizing a read signal from a data storage media is disclosed. An analog output signal is equalized by reading the data storage media using an analog equalization filter. The analog output of the analog equalization filter is converted to a raw digital output signal. The raw digital output signal is processed to detect and correct an error in the raw digital output signal. The error is detected and an adjustment is made to the boost of the analog equalization filter according to the error detected.

Abstract: An addressable circuit configured to control a definition of an addressable range for the circuit. The circuit may comprise at least one register, at east one flag, an input and control logic. The register may be configured to define a range used for determining an addressable range for the circuit. The flag may be configured to define whether a predetermined range is to be inverted for determining the addressable range for the circuit. The input may be configured to receive an address for an access to the circuit. The control logic may be configured to process the received address to determine whether the received address is within the addressable range for the circuit, the control logic being responsive to the register and to the flag for determining the addressable range therefrom.

Abstract: The invention contemplates a system and method for efficient instruction prefetching based on the termination of loops. A computer system may be contemplated herein, wherein the computer system may include a semiconductor memory device, a cache memory device and a prefetch unit. The system may also include a memory bus to couple the semiconductor memory device to the prefetch unit. The system may further include a circuit coupled to the memory bus. The circuit may detect a branch instruction within the sequence of instructions, such that the branch instruction may target a loop construct. A circuit may also be contemplated herein. The circuit may include a detector coupled to detect a loop within a sequence of instructions. The circuit may also include one or more counting devices coupled to the detector. A first counting device may count a number of clock cycles associated with a set of instructions within a loop construct.

Abstract: The present invention is directed to the present invention is directed to an adhesive pad with electromagnetic compatibility (EMC) characteristics. An adhesive pad suitable for bonding electrical components may include a thermal bonding adhesive material and a lattice interlayer. The adhesive material is suitable for being disposed between the first electrical component and the second component, the thermal bonding adhesive bonding the first electrical component to the second component. The lattice interlayer is included within said thermal bonding adhesive material, the lattice interlayer having electromagnetic capability (EMC) shielding characteristics.

Abstract: An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber.

Abstract: A method of reducing power rail transients on integrated circuits. The power rail transients are reduced by controlling clock skew in a manner which minimizes dI/dT current demands. The method provides that the phase of the clock to latches/flip flops is shifted in order to spread out the number of simultaneous switching elements. By controlling the number of simultaneous switching devices, a significant reduction in time rate of current demanded from the power rails can be achieved, thereby reducing the magnitude of VSS/VDD voltage transients due to parasitic inductances and resistances supplying power to the integrated circuit. Theoretically, the entire timing spread of the slack graph for clock skew can be used to control the number of simultaneous switching devices.

Abstract: Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the metal lines and over protective caps on the lines. After the formation of such low k material between the lines and over the caps, standard k dielectric material is deposited over the low k layer as a planarizing layer over low portions of the low k layer between the lines which may be lower than the top of the caps on the lines to prevent further etching or dishing of the low k layer of during planarizing. The structure is then planarized to bring the low k dielectric material down to the tops of the protective caps on the metal lines. A layer of standard k silicon material is then formed over the planarized low k layer and the caps to allow via formation without passing through the low k layer to avoid via poisoning.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises one or more master amplifiers and a plurality of control amplifiers. The first circuit may be configured to generate a plurality of control signals in response to (i) a first signal related to a desired gain and (ii) a second signal related to a known reference. The second circuit may be configured to generate an output signal in response to (i) an input signal and (ii) the plurality of control signals. The output signal may be amplified with respect to the input signal.