Abstract: A power ground short circuit with adjustable activation delay and activation time period eliminates latent voltages in the power down/ off discharging circuitry. The circuit uses an internal back up power storage device to supply power on power down. A comparator determines when the power down condition occurs. Two timers are used to generate an activation signal for a charge pump. The charge pump is responsible for turning on a pair of transistors which bring the power bus voltage down to a zero level. A slew rate detector enables the comparator.

Abstract: A system for identifying a substrate based on indicia formed in a surface of the substrate. The method includes forming the indicia having edge features and substantially flat features. The indicia is illuminated with incident illumination from an illumination source while moving the illumination source relative to the substrate, thereby scanning the incident illumination over the indicia. Reflected illumination having a first intensity level is received from the edge features of the indicia, and reflected illumination having a second intensity level is received from the substantially flat features of the indicia. The reflected illumination is detected to produce at least one output signal having a first amplitude level corresponding to the first intensity level and a second amplitude level corresponding to the second intensity level. The output signal is processed based at least in part upon the first and second intensity levels to form at least one image portion of the indicia.

Abstract: An integrated circuit topography is provided which includes at least two rows of bonding pads. Each row of bonding pads is attributed a row of probe pads. One row of probe pads is contained within the scribe area and suffices as a sacrificial row of probe pads. The other row of probe pads is placed toward the interior of the integrated circuit. The rows of bonding pads and probe pads extend along parallel axis around all four sides of the integrated circuit. Every other bonding pad within one row of bonding pads is connected to every other probe pad within the scribe area, and every other bonding pad within the other rows of bonding pads is connected to every probe pad within the row of probe pads interior to the integrated circuit. This allows a fan-out configuration of the bonding pads to probe pads for purposes of probing electrical performance of the integrated circuit without having to use selected ones of the bonding pads.

Abstract: A process is provided for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes including one or more organofluoro silanes characterized by the absence of aliphatic C—H bonds. In one embodiment, the process is carried out using a mild oxidizing agent. Also provided is a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material for use in an integrated circuit structure containing silicon atoms bonded to oxygen atoms, silicon atoms bonded to carbon atoms, and carbon atoms bonded to fluorine atoms, where the dielectric material is characterized by the absence of aliphatic C—H bonds and where the dielectric material has a ratio of carbon atoms to silicon atoms of C:Si greater than about 1:3.

Abstract: An integrated circuit device is disclosed having a boundary scan chain and a hardwired BIST unit that is configurable via the control circuitry for the boundary scan chain. In one embodiment, the device includes application logic, a BIST unit, a boundary scan chain, a register, and a test access port. The application logic is the logic that provides the intended function of the chip. The BIST unit is configured to apply test patterns to the application logic to verify its functionality. The boundary scan chain is configured to sample input signals to the application logic and to control output signals from the application logic. The register stores an operational mode parameter for the BIST. The test access port provides external access to the boundary scan chain and the register, and is configured to control a clock signal to the BIST unit in accordance with the BIST operational mode parameter.

Abstract: A procedure and processor are disclosed for avoiding lengthy delays in debug procedures during access by a memory mapped peripheral device. The processor includes in-circuit emulation means comprising one or more scan chains or serially connected registers for access by an external host computer system. The procedure comprises: a) the host computer system carrying out a debug procedure via said scan chains, and selectively interrupting such debug procedure for access to a peripheral memory mapped device; b) the host computer system writing into an area or memory of the processor a program for reading and/or writing data at a specified memory location; and c) the host computer system causing said processor to run said program, and then to return to said debug procedure.

Abstract: A method and apparatus for maintaining a fax transmission over a relay network that includes at least first and second portions and a relay portion that couples the first and second portions to each other. At a second gateway connecting the second portion to the relay portion, data frames received over the relay portion are processed to determine if they are corrupted, and signals are sent back to a first gateway to resend any data frames that are corrupted. The first gateway connects the first portion to the relay portion.

Abstract: A video system is disclosed that processes OSD images and displays the OSD images on a display. At least some of the OSD images are represented by data sets that do not include a color palette. Each OSD data set includes a header comprising multiple bits of status and control information. One of the control bits indicates whether the OSD data set includes a color palette. Preferably that control bit is set to indicate no color palette in present and cleared to indicate the inclusion of a color palette in the OSD data set. By not including a color palette in an OSD data set, the corresponding OSD image can be represented with a smaller data set and can be transferred across a bus with a smaller bandwidth. If the control bit is set, indicating the absence of a color palette in the OSD data set, a color palette included in another OSD data set is used instead to draw the desired OSD image.

Abstract: Embodiments of the invention include a method for blanket ion implanting a semiconductor substrate surface to induce uniform damage over desired portions of the surface thereby reducing non-uniform etch effects caused by the varying etch rates of surface materials and conditions during surface cleaning. The invention includes providing a semiconductor substrate having gate oxide regions and a sacrificial oxide layer of a predetermined thickness formed thereon. The surface of the substrate is pattern masked to reveal openings in the gate oxide regions and ion implanted through the openings in the pattern mask to form gate oxide regions. The pattern mask is removed from the substrate and a blanket implantation of the sacrificial oxide layer is performed. The substrate is then cleaned to remove the sacrificial oxide layer leaving the substrate in readiness for further processing.

Abstract: A method and apparatus in a source node for transmitting data to a target node. Responsive to a request to transmit data to the target node, a determination is made as to whether a selected period of time has passed without data transmitted from the source node being received by the target node. Responsive to detecting the selected period of time has passed without data transmitted from the source node being received by the target node, a determination is made as to whether space is available in the target node to receive the data. Responsive to a determination that space is unavailable in the target node, generating an indication that the target node is blocked is generated.

Abstract: A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage.

Abstract: A system controls reproduction of a video transmission between a transmitter and a receiver. The system includes an encryptor with an offset generator adapted to receive the encrypted frame key and to generate a sequence, of pseudo-random values for the color component; and an adder coupled to the offset generator and to the color component signal for providing an encoded color component signal. The system also includes a decryptor with a decryptor offset generator adapted to receive the encrypted frame key and to generate a decryptor pseudo-random value for the color component; and a subtractor coupled to the offset generator and to the color component signal for subtracting the offset signal from the color component signal.

Abstract: In the context of a DVD-RAM read-type architecture in which an optical storage medium (20) makes use of an eccentric wobble (164) to attain synchronisation information, a wobble PLL (179) is held in an acquired state whenever header regions (32, 33) embossed at regular intervals across the optical storage medium (20) are detected. More specifically, large dc variations associated with voltage spikes caused by header regions (32, 33) are scaled (260) relative to a dynamically varying amplitude envelope of the extracted wobble signal (164), such as to identify a start location (300) for each header region. The wobble PLL (179) is effectively allowed to free-run and hold state during periods of header, thereby mitigating the likelihood that the wobble PLL will loose lock during the header regions.

Abstract: Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.

Abstract: An integrated circuit having functional logic that provides system access to test access port controlled built-in-self-test logic is provided. The integrated circuit includes a test access port controller having an enable output and a status input. A built-in-self-test controller having an enable input, a status output, one or more random access memory cell controller outputs and one or more random access memory cell inputs is also provided. A functional logic interface is connected to the functional logic, the test access port controller enable output, and the built-in-self-test controller enable input, and allows a built-in self-testing sequence to be initiated from the test access port controller or the system.

Abstract: A variable gain amplifier includes a differential transconductor, a differential gain stage, a DC compensation circuit and first and second load resistors. The differential transconductor has first and second differential voltage signal inputs and first and second differential current outputs. The differential gain stage selectively steers current from the first and second differential current outputs to first and second variable current outputs, respectively, and to first and second compensation current outputs, respectively, based on a differential gain control input. The first and second load resistors are coupled to the first and second variable current outputs, respectively. The DC compensation circuit combines current in the first and second compensation current outputs to form a DC compensation current and couples the DC compensation current to the first and second load resistors.

Abstract: A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam. The vertically configured structure may be a reduced vertical thickness of the severable portion, an elevated lower surface of the severable portion above adjoining portions of the fuse link, a protrusion which supports the severable portion at a height greater than a height of the adjoining portions of the fuse link, flowing the melted severable portion down sloped surfaces away from a break point, and a propellent material beneath the severable portion which explodes to ablate the severable portion.

Abstract: A method for fabricating a semiconductor package having a 2-layer substrate, which includes an array of solder balls, is disclosed. The method includes patterning signal traces on a top layer of the substrate and identifying groups of signal traces to isolate. According to the present invention, a grounded isolation trace is then patterned adjacent to one of the groups of traces to isolate the signal traces, thereby providing noise shielding. In a preferred embodiment, the grounded isolation trace is provided with multiple vias, rather than only one. In a further aspect of the present invention a row of solder balls is connected together and to ground to create a bottom-layer isolating ground trace to further reduce noise. The bottom-layer isolating ground trace may be connected to the top-layer isolating ground trace using a via.

Abstract: A message that has its energy spread over a frame of encoded data is decoded. First, encoded data are received so as to obtain a quantity of the encoded data that is less than all the encoded data in the frame and also is less than all the encoded data representing the message. Then, the quantity of encoded data received is supplemented, without receiving additional encoded data, so as to obtain a frame of data. Typically, the data will be supplemented by zero padding the data, such as by initializing a frame buffer to all zeros and then overwriting the zero data with actual data as it is received. Finally, ordinary frame decoding is performed on the frame of data so generated, in order to decode the message.

Abstract: A process for selectively reinforcing portions of a low k dielectric material which comprises first forming a low k dielectric layer, then forming openings in the low k layer in portions of the low k layer needing reinforcement, and then filling the openings with reinforcing material, preferably reinforcing material having a higher Young's modulus of elasticity than the low k dielectric material. Such selective reinforcement of certain portions of low k dielectric material may comprise selectively reinforcing the low k dielectric material beneath the bonding pads, with reinforcing material. The low k dielectric material may be reinforced by openings in the low k dielectric material formed beneath portions of the low k dielectric layer where a capping layer will be formed over the low k dielectric material. Subsequent formation of the capping layer will simultaneously fill the openings with capping material, which may then also function as reinforcement material in the openings.