Abstract: A method of forming an electrically conductive interconnect on a substrate. An interconnection feature is formed on the substrate, and a first barrier layer is deposited on the substrate. The first barrier layer consists essentially of a diamond film. A seed layer consisting essentially of copper is deposited on the substrate, and a conductive layer consisting essentially of copper is deposited on the substrate. Thus, by using a diamond film as the barrier layer, diffusion of the copper from the conductive layer into the material of the substrate is substantially reduced and preferably eliminated.

Abstract: A programmable self time circuit for controlling bit line separation in a memory includes multiple self time word lines, each of which is connected to at least one core cell of the memory for activating the cell. The self time word lines have enable signals that can either be programmed on/off, or can be externally controlled for variation of the amount of bit line separation developed during a memory access.

Abstract: A method for de-interlacing a decoded video stream comprising the steps of (A) defining a sampling period, (B) sampling the decoded video stream during the sampling period to define one or more parameters, (C) adjusting a threshold and a level of the decoded video stream used in processing, in response to the one or more parameters, (D) filtering the decoded video stream using a filter tool selected from a plurality of filters, in response to the one or more parameters.

Abstract: In a multi-directional orthogonal frequency division modulation (OFDM) communication system, for example, on a digital subscriber line, an uplink channel is provided by a first group of the OFDM sub-channels (sub-carriers), and a downlink channel is provided by a second group of the OFDM sub-channels (sub-carriers). In one aspect, communication efficiency is improved by controlling the relative number of sub-channels allocated to each group, and hence controlling the capacity of the channels dynamically. Preferably, the relative capacities are controlled in response to demand for channel capacity. In another aspect, the orthogonality of the sub-carriers generated by different transmitters is improved by providing a frequency and/or time synchronising signal for providing reference frequency and timing.

Abstract: An arrangement for planarizing a surface of a semiconductor wafer. The arrangement includes a planarizing member having a planarizing surface configured to be (i) positioned in contact with and (ii) moved relative to the surface of the semiconductor wafer so as to remove material from the surface of the semiconductor wafer such that the surface of the semiconductor wafer is planarized. The arrangement also includes an adherence promoting ligand chemically bonded to the planarizing surface of the planarizing member. The arrangement further includes an abrasion particle chemically bonded to the adherence promoting ligand such that the abrasion particle is attached to the planarizing surface of the planarizing member. The arrangement also includes a conditioning bar having a conditioning portion positioned in contact with a wafer track defined on the planarizing member. The conditioning portion is configured so that the conditioning portion extends completely across the wafer track.

Abstract: Forward error correction apparatus and methods are described. A forward error correction method includes: (a) computing syndromes values; (b) computing an erasure location polynomial based upon one or more erasure locations; (c) computing modified syndromes based upon the computed erasure location polynomial and the computed syndrome values; (d) computing coefficients of an error location polynomial based upon the computed modified syndromes; (e) computing a composite error location polynomial based upon the computed coefficients of the error location polynomial; (f) computing a Chien polynomial based upon the computed composite error location polynomial; (g) performing a redundant Chien search on the computed composite error location polynomial to obtain error location values; and (h) evaluating the computed Chien polynomial based upon the error location values to obtain error and erasure values.

Abstract: A method for calculating skew associated with providing a signal to a capacitive load along a first and second wire. The method includes steps of calculating a skew error which would result if the Elmore Model were used to calculate delays using the actual length of the wires, calculating a new effective length for the second wire based on the error which has been calculated, using the Elmore Model to calculate an effective delay which would be associated with providing the signal to the capacitive load along the new effective length of wire, and calculating skew using the effective delay which has been calculated. Preferably, the new effective length for the second wire is calculated by considering the actual lengths of the first and second wires, the capacitance of a unit length of wire and the capacitance of the capacitive load.

Abstract: Methods for calculating a total capacitance of a metal wire in an integrated circuit is disclosed. In the present invention, a library containing predetermined wiring topologies is created. Each of the wiring topologies has an associated capacitive value. After extracting a layout topology of a segment of the metal wire, the layout topology is used to find and extract one of the predetermined wiring topologies in the library that corresponds to the layout topology. The associated capacitive value for the extracted wiring topology is used to calculate the total capacitance of the metal wire.

Abstract: A system and a method are provided for preventing damage to wafers arranged in a wafer cassette. In particular, an apparatus is provided to protect wafers arranged in a wafer cassette during insertion of a wafer into the cassette. In one embodiment, the apparatus may be a separate entity from the wafer cassette. In this manner, the apparatus may be situated about the cassette such that the wafers arranged in the cassette are protected during insertion of a wafer. In another embodiment, the wafer cassette itself may be adapted to partially cover and protect the wafers arranged in the cassette during insertion of a wafer. Consequently, a method is provided using either embodiment of the apparatus. In particular, the method may include inserting a wafer into a wafer cassette by shielding one or more slots of the cassette, exposing a designated slot of the cassette, and inserting a wafer into the designated slot.

Abstract: Provided are systems and techniques for optimizing an integrated circuit design, in which a critical zone is identified in an integrated circuit design and a plurality of alternative identities are applied in the critical zone in order to obtain a corresponding plurality of outcomes. Alternative representations are then identified as those of the plurality of outcomes pursuant to which at least one of ramptime and timing are improved, and a best one of the alternative representations is selected to replace into the critical zone based on specified priorities which include: (i) selecting based on reduction in ramptime violation; (ii) selecting from among alternative representations that preserve cell area based on timing improvement; and (iii) if all alternative representations increase cell area, selecting based on an evaluation of a relationship between timing decrement and area increment.

Abstract: A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlying the first dielectric layer, a capacitor dielectric section overlying the first capacitor plate, and a fuse barrier section overlying and between the first and second fuse electrodes are formed simultaneously. In a conductive layer overlying the second dielectric layer, a second capacitor plate overlying the capacitor dielectric section, and a fuse overlying the fuse barrier section and contacting the first and second fuse electrodes are formed simultaneously. The capacitor dielectric section and the fuse barrier section may be defined simultaneously by selectively removing portions of the first dielectric layer during a single etching step.

Abstract: Provided is an analog-to-digital converter that includes a first analog-to-digital conversion (ADC) stage connected to input a first analog signal and a second ADC stage connected to input a second analog signal produced by the first ADC stage. A tone detector enables the second ADC stage from a disabled state when a first condition indicating the presence of a high-level interference tone is satisfied and disables the second ADC stage from an enabled state when a second condition indicating the absence of a high-level interference tone is satisfied.

Abstract: A process for forming a non-porous dielectric diffusion barrier layer on etched via and trench sidewall surfaces in a layer of porous low k dielectric material comprises exposing such etched surfaces to a plasma formed from one or more gases such as, for example, O2; H2; Ar; He; SiH4; NH3; N2; CHxFy, where x=1-3 and y=4-y; H2O; and mixtures of same, for a period of time sufficient to form from about 1 nanometer (nm) to about 20 nm of the non-porous dielectric diffusion barrier layer which prevents adsorption of moisture and other process gases into the layer of porous low k dielectric material, and prevents degassing from the porous low k dielectric material during subsequent processing.

Abstract: A method for eliminating scan hold time failures of a scan chain. The method uses information resulting from the distribution of a clock throughout an integrated circuit. In particular, a scan chain is reordered according to the results of the distribution of the clock signal. The distribution of the clock signal provides groups of sequential circuit elements that form the scan chain. The method also includes reordering the sequential circuit elements within at least one group according to a clock skew of the clock signal within the at least one group. The method further includes ordering the groups according to a clock skew of the clock signal between the groups.

Abstract: A capping layer of an insulator such as silicon nitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon nitride caps on the metal lines. After the formation of such low k silicon oxide dielectric material between the closely spaced apart metal lines and the over silicon nitride caps thereon, a second layer of silicon nitride is deposited over the layer of low k silicon oxide dielectric material.

Abstract: A controller generally comprising a DMA engine, a processor, and a circuit. The DMA engine may be configured to copy from a system memory to a local memory. The processor may be configured to process a message written in the local memory. The circuit may operate independently of the processor. The circuit may be configured to (i) monitor writes to the local memory for the message having a first pointer and (ii) program the DMA engine to copy a first buffer identified by the first pointer in response to the first pointer having a non-null value.

Abstract: Constant pins are determined in a combinational circuit by associating an input of a combinational circuit with a first variable and a second variable, with the second variable being the complement of the first variable. For a first logical cell interconnected to such input, a first mathematical representation and a second mathematical representation are computed. The first mathematical representation is a function of the operation of the first logical cell and a function of the first variable, and the second mathematical representation is a function of the operation of the first logical cell and a function of the second variable. A determination is then made as to whether one of the first and second mathematical representations is equal to a constant.

Abstract: An integrated circuit that includes an improved architecture that reduces the interface between different blocks by minimizing the wire connections between the two blocks. Specifically, the two blocks are structured to transfer data between the two blocks using only the data bus and a common clock, thus eliminating the need for an address bus. Each block contains data registers used for storing data. The data registers in one block correspond to the registers in the second block, with each block being aware of the memory structure of the other block. When one block needs data from the data registers of the other block, it requests the data and the sending block places the contents of its data registers on the bus sequentially. The requesting block reads the data from the data bus at the appropriate time by counting the number of clock cycles from the time that the data was requested.

Abstract: A metal wire for a feature of a cell is extended using a grid based on a metal layer of the cell. Each grid element is assigned an “F” designator representing the metal wire being extended, an “E” designator representing blockages to extension of the metal wire, such as metal wires of other features, or a “U” designator representing grid elements that are neither F-designated, nor E-designated grid elements. U-designated grid elements that are neighbors to E-designated grid elements are identified. A minimum length path is defined through the U-designated grid elements that are not neighbors to E-designated grid elements between the cell boundary and a F-designated grid element.

Abstract: A method and system for allocating and freeing memory in an electronic system allocates available memory by including at least one or more flags that indicate the size and status of the allocated segment in the same area in which the segment is allocated. A free portion in the available memory is searched such that the free portion is sufficient to accommodate the requested segment. Upon finding a free portion, a new segment is created in the free portion where the new segment includes an allocated segment equal in size to the requested segment and further includes a segment area that accommodates at least one flag of the allocated segment such that the segment area is adjacent to the allocated segment. At least one flag of the allocated segment is set, and may include a size flag or a status flag that indicates whether the allocated segment is occupied and whether the allocated segment is the last segment.