Abstract: An apparatus for detecting failures in electrical connections between an integrated circuit package substrate and a circuit board. The substrate has substrate electrical contacts that are electrically connected one to another in first sets in a first region of the substrate. The circuit board has circuit board electrical contacts that are electrically connected one to another in second sets in a second region of the circuit board. The substrate electrical contacts align with and make electrical contact with the circuit board electrical contacts. The first region of the substrate aligns with the second region of the circuit board when the substrate electrical contacts make electrical contact with the circuit board electrical contacts. The first sets of substrate electrical contacts form chains of electrical contacts with the second sets of circuit board electrical contacts. The chains of electrical contacts loop back and forth electrically between the substrate and the circuit board.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: The present invention discloses a novel method and apparatus for making a jitter transfer function of a phase-locked loop independent from the data transition density. The present invention is further discloses a phase-locked loop which has a loop bandwidth and a loop gain in the passband which are both independent from the received data patterns. By making the loop bandwidth independent of the received data pattern, the noise filtering performance of the phase-locked loop may be optimized.

Abstract: A method for characterizing cell interconnect delay is disclosed that may be included in a library for use with logic design tools. A method of characterizing cell interconnect delay includes the steps of (a) receiving as inputs a plurality of input ramptimes and a plurality of interconnect lengths for a selected cell, and (b) calculating an output ramptime and a total cell delay including a cell delay and an interconnect delay for each of the plurality of input ramptimes for each of the plurality of interconnect lengths for the selected cell from the inputs.

Abstract: The present invention provides a divider circuit for frequency division of input clock signals, and a method operating and a phase-locked loop (PLL) circuit incorporating the same. In one embodiment, the divider circuit includes a counting subcircuit configured to count rising and falling edges of an input signal. In addition, the divider circuit includes, a signal generator configured to provide an output signal by performing an operation on the count of the rising and falling edges of the input signal based on a divisor control signal.

Abstract: A method of estimating the number of available transit connections, or porosity, of a hardmac for a logic design routing tool includes the steps of calculating a total metal layer capacity of a hardmac, calculating an absolute porosity of the hardmac from the total metal layer capacity and an internal connection density, and calculating a relative porosity of the hardmac from the total metal layer capacity and the absolute porosity.

Abstract: A method of testing an integrated circuit. The thermal energy of the integrated circuit to adjusted to a first temperature, and a first set of electrical characteristics of the integrated circuit are sensed at the first temperature. The first set of electrical characteristics are recorded in association with an identifier for the integrated circuit. The thermal energy of the integrated circuit is adjusted to a second temperature, and a second set of electrical characteristics of the integrated circuit are sensed at the second temperature. The electrical characteristics of the second set correspond to the electrical characteristics of the first set. The second set of electrical characteristics are also recorded in association with the identifier for the integrated circuit.

Abstract: A method for performing timing driven interconnect estimation analysis is disclosed. The method includes collecting data only from timing critical paths of at least one previous design, and generating statistical data based on a net length distribution of the timing critical paths. A wire load model is then generated for a new design from the statistical data.

Abstract: The present invention selects parts of an integrated circuit description for resynthesis and then prepares those parts for resynthesis. Initially, a resynthesis goal is input, with the resynthesis goal having been selected from a set of possible resynthesis goals. Plural buffer and/or logic trees in the integrated circuit description are then selected based on the resynthesis goal, and information for each of the selected trees is obtained and stored. The tree information includes: (i) a description of each tree cell, including cell types, cell coordinates, and flips and angles of the tree cell, (ii) a description of each input net, (iii) a signal arrival time for each input net as a function of a capacity of such input net, (iv) coordinates of each pin driving each input net, and (v) a maximum capacity of each input net that will prevent such input net from having a timing violation.

Abstract: A method for fabricating a microstrip package to optimize signal trace impedance control is disclosed. The method includes patterning a plurality of signal traces on a multilayer substrate, and patterning a plurality of guard traces on the multilayer substrate, that are interspersed alternately among the signal traces to provide noise shielding between the signal traces. In a further embodiment, the traces are patterned on the substrate with a width that is adjusted at different locations based on the presence the guard traces to enable the package to meet a particular impedance requirement.

Abstract: A transconductance continuous time filter circuit comprising a first differential pair of transistors (328 and 330), and at least one pair of tuning transistors (326 and 332). Each of the tuning transistors (326 and 332) may be coupled via a respective switching transistor (346 and 348) to a supply line, with the gate electrodes of the switching transistors (346 and 348) being coupled to a control line. The switching transistors (346 and 348) may be turned on or off to couple or uncouple the tuning transistors (326 and 332) from the first differential pair of transistors. The effective width of the differential pair may also be varied such that the transconductance and hence the cut-off frequency of the filter circuit.

Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished.

Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.

Abstract: A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer.

Abstract: A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.

Abstract: A system for interconnecting a plurality of interdependent fiber channel loops or fabrics. The system preferably comprises a first server which includes a PCI bus and a fibre channel to PCI bus adapter for each one of the plurality of the independent fibre channels. Each fibre channel to PCI bus adapter is configured to connect one of the plurality fibre channels to the PCI bus at the first server. The plurality of independent fibre channels then communicate with each other across the PCI bus of the first server utilizing the intelligent I/O (I2O) routing of the fibre channel to PCI bus adapters. The plurality of fibre channels are configured to communicate with the other fibre channels, as well as the first server via the PCI bus. This system can be configured such that any one of the plurality of fibre channels can include one or more devices connected thereto in addition to the first server.

Abstract: A self-timing memory circuit with supply degradation compensation comprising a first self-timing circuit and a second self-timing circuit. The first self-timing circuit may be configured to generate a first signal that may be minimally affected by power supply degradation and/or variation. The second self-timing circuit may be configured to generate a second signal, where an effect of the power supply degradation and/or variation on the second signal is maximized.

Abstract: A method of fabricating an integrated circuit using photolithography and an antireflective coating. An antireflective coating is formed on a substrate wherein the antireflective coating is electrically polarizable. A photoresist coating is formed on the antireflective coating on a side opposite from the substrate and the photoresist is exposed to activating radiation. The antireflective coating is subjected to an applied electric field at substantially the same time as the photoresist is exposed to activating radiation. The radiation absorption coefficient of said antireflective coating is increased and the refractive index of said antireflective coating is changed to be substantially equal to the refractive index of said photoresist coating.

Abstract: A Register Transfer Language (RTL) annotation software tool that: (1) automatically calculates new RTL of a circuit to facilitate subsequent RTL level Engineering Change Orders (ECOs) on a circuit where gate level changes have occurred during layout; and (2) automatically calculates a gate level netlist that corresponds to the RTL ECO which can be fed to modern layout tools with minimal disruption to the existing layout. In a preferred embodiment, the tool is software driven, iterative, and tracks any changes that need to be made for any given circuit described by a hardware description language (HDL) though a series of intermediate and preliminary data files. The software receives input in the way of user input, constraints, and an RTL description for a pre-ECO circuit, and outputs the post-layout annotated RTL description.

Abstract: A source pulsed, dynamic threshold complementary metal oxide semiconductor static random access memory dynamically controls cell transistor threshold voltage to increase cell stability, decrease cell standby power, and reduce cell delay. A memory cell includes a low storage node and a high storage node wherein the low storage node is driven below Vss during a read access and the high storage node is driven above Vdd during the read access.