Abstract: A process for forming an integrated circuit structure characterized by formation of an improved barrier layer for protection against migration of copper from a copper-containing layer into low k dielectric material while mitigating undesired increase in dielectric constant and mitigating undesirable interference by materials in the barrier layer with subsequent photolithography.

Abstract: This invention comprises an improved method of planarizing, an integrated circuit formed onto a semiconductor substrate and the planarized semiconductor substrate. Improved planarity is accomplished through the use a first and second stop layer separated by a filler layer. A first stop layer is used to define active and trench regions. A filler layer is then applied over the surface of the substrate and a second stop layer is applied on top of the filler layer. The second stop layer is patterned through etching. The pattern etched into the second stop layer is used to control chemical mechanical polishing that planarizes the surface. Patterns can be a reverse image of an active mask or a continuous pattern. In addition CMP can be used to create a condition of equilibrium planarity before the second stop layer is applied. The stop layers can comprise polysilicon, silicon nitride, or another material that is harder than a dielectric oxide material used as filler material.

Abstract: The present invention involves a method for determining constant pins in a combinational circuit. The method comprises the steps of associating an input of a combinational circuit with a first variable and a second variable, wherein said second variable is the compliment of said first variable, computing for a first logical cell interconnected to said input a first canonical representation, wherein said first canonical representation is a function of the operation of said first logical cell and a function of said first value, computing for said first logical cell a second canonical representation, wherein said second canonical representation is a function of the operation of said first logical cell and a function of said second value, determining whether one of said first and second canonical representations is equal to zero.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first signal and a second signal in response to (i) a select signal, (ii) a first difference signal and (iii) a second difference signal. The second circuit may be configured to present a modulated output signal in response to the first signal, the second signal and a control signal. The first circuit may alternately operate on one of either (i) the first difference signal or (ii) the second difference signal. In one example, the present invention may be implemented as a SECAM video encoder.

Abstract: An improvement in the formation of low dielectric constant carbon-containing silicon oxide dielectric material by reacting a carbon-substituted silane with an oxidizing agent is described, wherein the process is carried out in the presence of a reaction retardant. The reaction retardant reduces the sensitivity of the reaction to changes in pressure, temperature, and flow rates, and reduces the problem of pressure spiking, resulting in the formation of a deposited film of more uniform thickness across the substrate as well as a film with a smooth surface, and a reduction of the amount of carbon lost during the reaction.

Abstract: A low threshold voltage MOS device on a semiconductor substrate is disclosed. The substrate has an upper surface, and a first well region is disposed in said semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The first well region includes a dopant of a first conductivity type having a first average dopant concentration. Source and drain regions of a second conductivity type are laterally spaced from each other and are disposed in the first well region, the source and drain regions extending downwardly from the semiconductor substrate upper surface a predetermined distance. A channel region comprising the first well region of the first conductivity type is disposed between the source and drain regions. The channel region also extends at least the predetermined distance below the semiconductor substrate upper surface.

Abstract: A mold for use in encapsulating an integrated circuit, wherein an encapsulant is injected into the mold during packaging of the integrated circuit. The improvement to the mold is a shaped member having an abutting surface for contacting a surface of the integrated circuit and thereby substantially preventing encapsulant from adhering to the surface of the integrated circuit, whereby the surface of the integrated circuit is left exposed. Because the surface of the integrated circuit is left exposed, the encapsulant used to encapsulate the integrated circuit does not form a thermal barrier between the integrated circuit and the exterior of the package. Thus, the packaged integrated circuit is able to more efficiently conduct heat away from the integrated circuit.

Abstract: A minimum core size of an integrated circuit chip is estimated for given parameters of an existing technology. The average wire length for the nets is calculated, and the centers of each cell are assigned to x,y coordinates to minimize wire length. The widths of routing channels between consecutive columns, and their associated core sizes are estimated based on the cell placement and the existing technology parameters. The minimum core size is identified from the estimated core sizes.

Abstract: A method and system for creating logical units (LUNs) in a RAID system by allocating proportional amounts of disk storage space to each LUN. Proportional allocation of disk space for different LUNs allows for the selective mapping of more data from the LUN to be mapped to some of the different disks to better optimize the I/O performance in a RAID system. The LUN is divided into a plurality segments or strips are allocated to predetermined disks in a predetermined proportional manner. A proportional create statement defines the proportional mapping and an intelligent RAID controller manages the proportional mapping of information.

Abstract: A method of generating a trace library includes the steps of receiving as inputs a plurality of technology dependent parameters and a trace template and generating a trace layout from the inputs.

Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.

Abstract: An integrated circuit package manufacturing process is described which reduces or eliminates the formation of voids in a molding compound between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. Electrically conductive vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the vias and the air space.

Abstract: A multiplication accumulation circuit (abbreviated as “MAC”) has five input buses that carry signals for operands A, B, C, D and E, a control bus that carries signals for controlling the operations performed on the received operands, and an output bus that carries a signal generated by the MAC. Each of operands A, B, C and D can be four different operands that are used as follows by the MAC: (1) to perform two multiplications simultaneously, and (2) to perform an addition of the products of the two multiplications and the fifth operand E, e.g. generate on the output bus a signal of value A*C+B*D+E. Alternatively, operands A and B can be, respectively, the upper and lower halves of a first double word to be used as a multiplicand. Similarly, operands C and D can be the upper and lower halves of a second double word to be used as a multiplier.

Abstract: A method of processing a semiconductor wafer and an associated semiconductor wafer arrangement which inhibits “punch through” and increases the yield of functional semiconductor wafers during the fabrication thereof is disclosed. A method of forming a semiconductor with a substrate and a feature on the surface of the substrate is disclosed: Forming a spacer layer that contacts the feature. A barrier layer of silicon nitride can be deposited on the surface. Contacting the barrier layer with the spacer layer, prior to removing the barrier layer. Align a contact void with the barrier layer and spacer layer. Align a contact void such that the etch properties of the barrier layer prevents “punch through”.

Abstract: A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.

Abstract: The present invention discloses a novel method and system for accessing a semiconductor device at multiple operating speeds. The novel method and system of the present invention allows access to a semiconductor device by a pipeline circuit in which modification of the pipeline circuitry is not required to achieve multiple operating speeds. An example of the invention may be the utilization of an internal clock to control internal pipeline which may allow adjustment of an effective operating speed of a semiconductor device.

Abstract: The present invention involves a method for reducing delay of a net. The method includes constructing a time-space grid, said time-space grid corresponding to a net, passing a wave through the time-space grid, said wave having a wave value, and inserting a buffer at a point on said time-space grid where insertion of the buffer increases a wave value. The buffer can be a negative buffer or positive buffer. Generally, a second wave is passed through the time-space grid simultaneously with the first wave. Typically, the second wave and the first wave are inverted.

Abstract: An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber.

Abstract: A method for creating a die that has some bond pads that are compatible with wire bonding and others that are compatible with solder bonding. A layer of copper is disposed over aluminum bond pads and selectively removed from those bond pads that are desired to be compatible with wire bonding.

Abstract: Techniques are described for fabricating a pair of &bgr;-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. In particular, the lengths of respective channel regions for the transistors are substantially the same, and portions of each gate electrode extending above a channel region include only dopants of a single conductivity type. The techniques can be incorporated into a standard CMOS process.