Abstract: The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output.

Abstract: A RAID system is provided in which the RAID controller of the system causes a predetermined number, N, of IO commands to be queued in a memory element, where N is a positive integer. After the N IO commands have been queued, the RAID controller writes N locks associated with the N IO commands in parallel to a service memory device. The RAID controller then writes N stripes of data and parity bits associated with the N IO commands to the PDs of the system to perform striping and parity distribution. If a catastrophic event, such as a power failure, occurs, the RAID controller reads the locks from the service memory device and causes parity to be reconstructed for the stripes associated with the locks. These features improve write performance while preventing the occurrence of data corruption caused by write holes.

Abstract: The present invention is directed to a method for implementing firmware in an expander system in such a way that a single hardware component (ex.—a chip) of the expander system may be presented as multiple virtual expanders to both upstream connected devices (ex.—HBAs) as well as downstream connected devices (ex.—disk drives).

Abstract: A method for pre-staging data includes obtaining a DST configuration of a virtual volume at a first point in time. The method also includes creating a Point-in-Time copy (PiT) in a destination storage pool when the virtual volume includes at least one PiT, or reconfiguring at least one virtual volume segment to contain a hot-spot. The virtual volume may or may not have PiTs. The method further includes recording the DST configuration, specifying the DST configuration be applied to the storage array at a second point in time, and applying the DST configuration to the storage array at the second point in time.

Abstract: Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.

Abstract: Several methods and a system to implement an efficient power supply management are disclosed. In one embodiment, an apparatus of a voltage supply includes a power supply providing a voltage. The apparatus includes an active supply module communicating with a supply voltage to a voltage bus through an ORing element. The apparatus also includes a redundant supply module providing an additional voltage to the voltage bus if the active supply module fails, through an additional ORing element. The redundant supply module may be coupled with the power supply in parallel with the active supply module. Further, the apparatus includes an automatic changeover module detecting a failure of the active supply module disabling the active supply module and enabling the redundant supply module to supply the additional voltage supply to the voltage bus. Further, the apparatus also includes a voltage bus coupled with a load.

Abstract: An apparatus comprises digitally controlled oscillator circuitry, feedback circuitry operatively coupled to the digitally controlled oscillator circuitry, and comparison circuitry operatively coupled to the digitally controlled oscillator circuitry and the feedback circuitry. The feedback circuitry, in response to a clock signal generated by the digitally controlled oscillator circuitry, generates a first digital value representing a detected phase of the clock signal for a given clock signal cycle. The comparison circuitry, in response to the first digital value and to a second digital value representing a reference phase, generates a phase error value. The phase error value is useable to generate a first digital control word provided to the digitally controlled oscillator circuitry for controlling a frequency associated with the clock signal.

Abstract: An expander device and method for transmitting serial input/output (SIO) data between an initiator device and a plurality of target devices. The expander device includes a processor/controller configured to receive a master data stream from an initiator device and to transmit a returning master data stream to the initiator device. The expander device includes a plurality of target master ports coupled to the processor/controller and configured to transmit split data streams to corresponding target devices coupled thereto and to receive returning split data streams from the target devices. The processor/controller splits the master data stream, based on its data, into a plurality of split data streams, and directs the split data streams to the target master ports based on the data in the split data streams. The processor/controller also assembles a plurality of returning split data streams into the returning master data stream and transmits the returning master data stream to the initiator device.

Abstract: A differential line driver with N-paralleled slices for driving an impedance-matched transmission line. Each driver slice is a modified H-bridge driver using low-voltage, high-speed transistors. By using a voltage-dropping first resistor in each slice, a high-voltage power supply that would normally damage the transistors can be used to power the driver and produce a differential output signal with peak-to-peak amplitudes that otherwise might not be possible. Each transistor in each driver slice has a resistor disposed between the transistor and the respective output node of the driver to enhance ESD protection of the transistors and, in combination with the first resistor, to impedance match the driver to the transmission line.

Abstract: Described embodiments provide a server for transferring data packets of streaming data sessions between devices. A redundant array of inexpensive disks (RAID) array having one or more stripe sector units (SSU) stores media files corresponding to the one or more data sessions. The RAID control module receives a request to perform the write operation to the RAID array beginning at a starting data storage address (DSA) and pads the data of the write operation if the amount of data is less than a full SSU of data, such that the padded data of the write operation is a full SSU of data. The RAID control module stores the full SSU of data beginning at a starting data storage address (DSA) that is aligned with a second SSU boundary, without performing a read-modify-write operation.

Abstract: Systems and methods for out of order memory management.

Abstract: A system for, and method of, generating block timing constraints and a timing model. In one embodiment, the system includes a hierarchical modeling tool configured to: (1) generate a model file, (2) receive at least one abstracted view margin, at least one timing environment margin and at least one operational margin for inclusion in the model file, (3) generate block implementation timing constraints employing the at least one timing environment margin and the at least one operational margin and (4) generate a block timing model employing the at least one abstracted view margin and the at least one operational margin.

Abstract: In order to provide a solution for performing priority arbitration, a mask and reset-mask are generated in concert with a priority arbitration scheme. A plurality of requestors may issue requests for a shared resource. The priority arbitration scheme may grant access to a single requestor for a single priority assignment period. The mask may assist the priority arbitration scheme to assign priority to the plurality of requestors by temporarily removing a subset of the plurality of requestors for a particular priority assignment period. If the mask allows for no allowable requestors during the priority assignment period, a reset-mask scheme is implemented to reset the mask to permit an increased number of requestors access to the priority arbitration scheme.

Abstract: Processing input/output requests may include: processing one or more input/output (IO) requests in a first IO queue associated with a first device group; detecting a queuing of one or more IO requests in a second IO queue associated with a second device group; pausing the processing one or more input/output (IO) requests in a first IO queue associated with a first device group upon a detection of a queuing of one or more IO requests in a second IO queue associated with a second device group; processing the one or more IO requests in a second IO queue associated with a second device group; and resuming the processing one or more input/output (IO) requests in a first IO queue associated with a first device group upon a completion of the processing the one or more IO requests in a second IO queue associated with a second device group.

Abstract: A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to bitlines associated with respective columns of the memory cells of the memory array. The sensing circuitry comprises, for at least a given one of the bitlines of the memory array, a sense amplifier configured to sense data on the given bitline, with the sense amplifier having at least one internal node and at least one output node. The sensing circuitry further comprises a latch circuit having a data input coupled to the output node and a control input coupled to the internal node, with the latch circuit being configured to latch sensed data from the output node responsive to a signal at the internal node.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal that is also utilized to cause the scan cells to form a serial shift register during scan testing. The clock gating circuitry may be used to determine whether a clock delay defect that causes a scan error during scan testing will also cause a functional error during functional operation, thereby improving yield in integrated circuit manufacturing.

Abstract: A RAID data storage system incorporates permanently empty blocks into each stripe, distributed among all the data storage devices, to accelerate rebuild time by reducing the number of blocks that need to be rebuilt in the event of a failure.

Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.

Abstract: A method, apparatus, and system of a software technique for improving disk write performance on raid system where write sizes are not an integral multiple of number of data disks are disclosed. In one embodiment, a method includes configuring a queue module to place an amount of data of a write operation into a data buffer module associated with a memory system if writing the amount of data to the memory system would generate a read-modify-write operation to occur, using the data buffer module to temporarily store the amount of data, writing the amount of data from the data buffer module to the memory system. The method may include algorithmically determining the amount of data to place in the data buffer module as a portion of the write operation that may cross a boundary between a striped sector unit (SSU) and/or an other SSU.

Abstract: A system, method, and computer program product are provided for reducing a rate of data transfer to at least a portion of memory. In operation, a rate of degradation of at least a portion of memory associated with a drive is determined. Furthermore, a rate of data transfer to the at least a portion of the memory is reduced, based on the determined rate of degradation.