Abstract: A decoder-implemented method for layered decoding that, when the decoder converges on a near codeword using an initial schedule, (i) selects a subsequent schedule from a schedule set based on the layer Lmaxb of the near codeword, which layer contains the greatest number of unsatisfied check nodes and (ii) re-performs decoding using the subsequent schedule. When used in an offline schedule-testing system, the layered-decoding method (i) identifies which schedules, out of a population of schedules, correctly decode a decoder input codeword and (ii) associates the identified schedules with the Lmaxb value of the near codeword.

Abstract: A multiple-port memory device having at least first and second ports each configured to support read and write operations. The multiple-port memory device further comprises a single-port memory device and control circuitry coupled between the first and second ports and the single-port memory device. The control circuitry is configured to multiplex input signals received over the first and second ports of the multiple-port memory device into respective input time slots of the single port of the single-port memory device, and to demultiplex output time slots of the single port of the single-port memory device into output signals that are supplied over the first and second ports of the multiple-port memory device.

Abstract: A digital modulation system provides enhanced multipath performance by using modified orthogonal codes with reduced autocorrelation sidelobes while maintaining the cross-correlation properties of the modified codes. For example, the modified orthogonal codes can reduce the autocorrelation level so as not to exceed one-half the length of the modified orthogonal code. In certain embodiments, an M-ary orthogonal keying (MOK) system is used which modifies orthogonal Walsh codes using a complementary code to improve the auto-correlation properties of the Walsh codes, thereby enhancing the multipath performance of the MOK system while maintaining the orthogonality and low cross-correlation characteristics of the Walsh codes.

Abstract: A system for, and method of, performing static timing analysis. In one embodiment, the system includes: (1) a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design and (2) an STA tool configured to derate the each of the cells based on the corresponding cell-based voltage supply.

Abstract: An adaptive filter configured to use multiple algorithm species that differ in the quality of echo suppression and respective burdens imposed on the computational resources of the host communication device. Depending on the available computational budget, the adaptive filter selects an algorithm species that, while supporting a relatively high quality of echo suppression, involves a relatively low risk of overwhelming the computational resources. The adaptive filter monitors changes in the available computational budget and, if appropriate or necessary, can change the algorithm species to maintain a quality of echo suppression that is optimal for the current computational budget. If a change of the algorithm species is initiated, then at least a portion of internal algorithm data from the previously running algorithm species might be transferred for use in the subsequent algorithm species.

Abstract: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate a thread of contexts for each task received by the packet classifier from a plurality of processing modules of the network processor. The scheduler includes one or more output queues to temporarily store contexts. Each thread corresponds to an order of instructions applied to the corresponding packet, and includes an identifier of a corresponding one of the output queues. The scheduler sends the contexts to a multi-thread instruction engine that processes the threads. An arbiter selects one of the output queues in order to provide output packets to the multi-thread instruction engine, the output packets associated with a corresponding thread of contexts. Each output queue transmits output packets corresponding to a given thread contiguously in the order in which the threads started.

Abstract: A system and method for providing memory bandwidth efficient correlation acceleration. A correlation accelerator or correlator (e.g., an X*Y correlator) can be configured in association with a processor of a wireless communication system for correlating an input signal data sequence (X) and its shifted versions with a reference data sequence. Shifted versions (including the 0-shifted or the original) with respect to the input signal data sequence can be generated for each column (Y columns) of a sliding window in the correlator in order to reduce an input bandwidth requirement. Each input signal data and the shifted versions can be concurrently multiplied with the reference signal data and the results can be summed together in order to generate an output signal data profile. The output signal data profile can be stored into an accumulator register in order to reduce an output bandwidth requirement.

Abstract: Techniques for forming a first electronic circuit including a plurality of instances of a repeatable circuit element include the steps of: obtaining a total number of instances of the repeatable circuit element in a design of an IC including the first electronic circuit and at least a second electronic circuit; and configuring at least one functional parameter of the first electronic circuit as a function of the total number of instances of the repeatable circuit element in the IC to thereby satisfy a prescribed minimum composite manufacturing yield of the IC and/or at least one specification of the IC under prescribed operating conditions.

Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

Abstract: A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.

Abstract: Described embodiments provide for authenticating a user request for access to at least a portion of an encrypted storage device. First, the request for access to at least a portion of the encrypted storage device is received. The request includes a plaintext password. A hash module generates a hashed version of the received plaintext password based on an authentication hash key. A hashed value of the generated plaintext password is retrieved from a key storage. A hash comparator compares the hashed version of the received plaintext password with the retrieved hashed value of the generated plaintext password. If the hashed version of the received plaintext password and the retrieved hashed value of the generated plaintext password are equal, the user is authenticated for access to at least a portion of the encrypted storage device. Otherwise, the user is denied access to the encrypted storage device.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: Described embodiments process hash operation requests of a network processor. A hash processor determines a job identifier, a corresponding hash table, and a setting of a traversal indicator for a received hash operation request that includes a desired key. The hash processor concurrently generates a read request for a first bucket of the hash table, and provides the job identifier, the key and the traversal indicator to a read return processor. The read return processor stores the key and traversal indicator in a job memory and stores, in a return memory, entries of the first bucket of the hash table. If a stored entry matches the desired key, the read return processor determines, based on the traversal indicator, whether to read a next bucket of the hash table and provides the job identifier, the matching key, and the address of the bucket containing the matching key to the hash processor.

Abstract: A method for robust preamble location and gate training in a Double Data Rate type Three (DDR3) computing environment. A single algorithm is employed to begin sampling a Data Strobe Signal (DQS) at a maximum delay value designed to fall within the driven region of a DQS. The method then begins sampling the DQS in a sequence of delay values from right to left. Each result of the sampling indicating a high state and a low state are stored as well as the occasions where the DQS transitioned from high to low indicating a rising edge. At a consecutive number of samples returning a low state, the method determines the preamble has been reached and discontinues sampling. The method retains the most recently stored rising edge as the first rising edge and configures the result for gate training.

Abstract: The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.

Abstract: Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.

Abstract: Methods and structure for an improved solid-state drive (SSD) for use in caching applications. An improved SSD comprises both volatile and non-volatile memory. The volatile memory provides improved performance as compared to present SSDs for use in caching application. The improved SSD senses impending failure of external power applied to the SSD and, while adequate power remains, copies cached data from the volatile memory to the non-volatile memory to retain the data through the power loss. In some embodiments, a local power source may be present to assure sufficient time for the SSD to save cached data in the non-volatile memory. Since the volatile memory (e.g., DRAM) is used for the primary caching function and the non-volatile memory is rarely used, performance, reliability and cost goals are achieved for write cache applications.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises calibration circuitry configured to vary a phase of a clock signal as a test pattern is written to the storage disk as part of a calibration procedure, and disk locked clock circuitry coupled to the calibration circuitry and configured to obtain phase lock between the clock signal and a timing pattern on a surface of the storage disk. The calibration circuitry is further configured to determine an initial phase update value to be applied by the disk locked clock circuitry in a control loop as the phase of the clock signal is varied as part of the calibration procedure.

Abstract: Methods and systems for two device failure tolerance in a RAID 5 storage system. Features and aspects hereof provide for allocating a spare storage device in the storage system for use with a standard RAID level 5 storage volume to form an enhanced RAID level 5 volume. Additional redundancy information is generated and stored on the spare storage device such that the enhanced RAID level 5 volume is operated by the storage controller so as to survive a failure of up to two of the storage devices of the enhanced volume. The allocated spare storage device may be reallocated by the storage controller for another purpose in which case the storage controller continues to operate the enhanced volume as a standard RAID level 5 volume that can only tolerate a single failure of a storage device of the volume.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises an inter-track interference detector configured to process a signal read from at least a given track of the storage disk via the read/write head in order to detect interference in that signal from at least one other track of the storage disk. The control circuitry further comprises an inter-track interference based head position controller configured to adjust the positioning of the read/write head responsive to the detected interference.