Abstract: Disclosed is a method and apparatus for testing devices that will be connected to a computer storage media device by generating a complex test waveform that emulates operation of the computer storage media device using at least one Graphics Processing Unit (GPU) and applying the generated complex test waveform to the device(s) being tested. The complex test waveform may be generated by calculating a plurality of discrete individual portions of the complex test waveform in parallel, in real-time, and continuously using the parallel processing features of the GPU(s). The discrete individual portions of the complex test waveform may be representative of various characteristics of the emulated computer storage media device operation such as operational characteristics of the computer storage media device, environmental effects on the computer storage media device, application of filters to the computer storage media device signal, etc.

Abstract: Described embodiments provide a memory manager for a network processor having a plurality of processing modules and a shared memory. The memory manager allocates blocks of the shared memory to requesting ones of the plurality of processing modules. A free block list tracks availability of memory blocks of the shared memory. A reference counter maintains, for each allocated memory block, a reference count indicating a number of access requests to the memory block by ones of the plurality of processing modules. The reference count is located with data at the allocated memory block. For subsequent access requests to a given memory block concurrent with processing of a prior access request to the memory block, a memory access accumulator (i) accumulates an incremental value corresponding to the subsequent access requests, (ii) updates the reference count associated with the memory block, and (iii) updates the memory block with the accumulated result.

Abstract: In one embodiment, a turbo equalizer is selectively operable in either first or second modes. In the first mode, layered (low-density parity-check (LDPC)) decoding is performed on soft-output values generated by a channel detector, where, for each full local decoder iteration, the updates of one or more layers of the corresponding H-matrix are skipped. If decoding fails to converge on a valid LDPC-encoded codeword and a specified condition is met, then LDPC decoding is performed in a second mode, where the updates of all of the layers of the H-matrix are performed for each full local decoder iteration, including the one or more layers that were previously skipped in the first mode. Skipping one or more layers in the first mode increases throughput of the decoder, while updating all layers in the second mode increases error correction capabilities of the decoder.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector.

Abstract: Methods and circuits in an application circuit to compensate for skew in the transmission of serial data between field programmable gate arrays (FPGAs) in the application circuit. A clock signal source external to both FPGAs generates a clock signal applied to both FPGAs. A transmitting FPGA generates a serial data stream comprising the current values of a plurality of signals within the transmitting FPGA and transmits the serial data stream based on its clock signal. The receiving FPGA receives the serial data stream and applies a programmed delay to the received serial data stream to compensate for skew in received serial data stream relative to its clock signal. The programmed delay value may be determined at initialization (or reset) of the FPGAs by transmitting synchronization data from the first transmitting FPGA to the receiving FPGA. The receiving FPGA adjusts a programmable delay while receiving synchronization data until it sense bit and word alignment relative to its clock signal.

Abstract: Various embodiments of the present invention provide systems and methods for determining a location of a spiral pattern. As an example, a location detection circuits is discussed that includes: a pattern detection circuit, a computation circuit, and a center determination circuit. The pattern detection circuit is operable to identify a subset of a series of data samples corresponding to a defined pattern, and to indicate a location of the identified subset of the series of data samples. The series of data samples corresponds to a spiral pattern. The computation circuit operable to sum an absolute value of each sample of the subset of the series of data samples to yield a sum. The center determination circuit operable to identify a location of the spiral pattern using the sum.

Abstract: In one embodiment of the present invention, a memory system is disclosed to include at least one initiator, a SATA device, and an improved bridge device configured to facilitate communication between the at least one initiator and the SATA device and having at least one input port and operative to receive information through the input port(s) from the initiators, the improved bridge device for processing a notification event wherein notification is sent to the at least one initiators during a notification event, and for performing an action, based on a an event, thereby facilitating ease of communication between the initiator and the SATA device.

Abstract: Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a servo address mark count circuit, a user sync mark count circuit, and an offset calculation circuit. The servo address mark count circuit is operable to provide: a first count corresponding to a first servo address mark within a first track of a storage medium, a second count corresponding to a second servo address mark within the first track, a third count corresponding to a third servo address mark within a second track of the storage medium, and a fourth count corresponding to a fourth servo address mark within the second track. The user sync mark count circuit is operable to provide: a fifth count corresponding to a first user sync mark within the first track, and to provide a sixth count corresponding to a second user sync mark within the second track.

Abstract: A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed.

Abstract: Methods and systems for reducing the signal path count between circuits within a SAS expander used for establishing SAS connections. The system comprises a SAS expander. The SAS expander comprises a plurality of link layer control circuits, each link layer control circuit adapted to communicatively couple with a SAS device. The SAS expander further comprises a connection manager communicatively coupled with the link layer control circuits for routing communications between the link layer control circuits. Each of the plurality of link layer control circuits is adapted to establish a SAS connection with another link layer control circuit through the connection manager by segmenting a plurality of interconnect signals into multiple data segments for sequential transmission to the connection manager, (e.g., without impacting the performance of the connection manager). The connection manager interprets the data segments to extract the plurality of interconnect signals to establish the SAS connection.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a lighting component and a mounting structure. The lighting component can include a light source, a plate, and a frame. The light source can include one or more lighting elements, such as light emitting diodes. The lighting component can be releasably secured to the mounting structure.

Abstract: A transmitter comprises indicator channel processing circuitry configured to process indicator channel codewords for transmission in a base station of a wireless system. The indicator channel processing circuitry performs a plurality of processing operations on the indicator channel codewords in a specified processing sequence, with the plurality of processing operations comprising at least modulation, scrambling, spreading and combining. In the specified processing sequence, the scrambling operation is performed for at least a given one of the indicator channel codewords prior to the modulation and spreading operations for that codeword or subsequent to the combining operation for that codeword. For example, the specified processing sequence may comprise the scrambling, modulation, spreading and combining operations performed in that order for at least the given codeword, or the modulation, spreading, combining and scrambling operations performed in that order for at least the given codeword.

Abstract: Various embodiments of the present invention provide systems and methods for data processing using variable scaling.

Abstract: In one embodiment, a method for signal processing is provided that uses an improved inversion to mitigate the imprecision introduced by fast approximate methods for division. An input signal is received and processed to generate a matrix M. The matrix M is inverted to generate an inverted matrix M?1. Matrix M is inverted by (i) decomposing the matrix M into a plurality of first sub-matrices, (ii) generating, based on the first sub-matrices and without any division operations, numerators for a plurality of second sub-matrices of the inverted matrix M?1, (iii) generating, based on the first sub-matrices and without any division operations, denominators for the second sub-matrices, and (iv) generating the second sub-matrices based on the numerators and denominators. The inverted matrix M?1 is processed to generate an output signal. Accordingly, a reduction in noise level from inaccuracy in division is achieved, and computational complexity is reduced.

Abstract: In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.

Abstract: A method for selecting a population of schedules of an n-layer decoder for offline schedule testing. The method identifies one or more triads, where a triad is a sequence of three layers where no layer is repeated. The method selects a set of schedules where each of the identified triads is contained in at least one schedule. The method associates each selected schedule with one or more key-layer values, where a key layer is the middle layer of a triad contained within the schedule.

Abstract: An electronic device includes an integrated circuit and a heat spreader. The integrated circuit includes a substrate with an active via located therein. The heat spreader includes a thermally conductive core. The active via is connected to a corresponding heat spreader via that passes through the thermally conductive core.

Abstract: An integrated circuit having a CAM array includes a plurality of CAM cells organized in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and a match line for each row connected to be shared by CAM cells in that row. The CAM array also includes a feedback circuit for each row connected to limit a discharge voltage for a corresponding match line in that row. In another aspect, a method of operating an integrated circuit having a CAM array includes organizing a plurality of CAM cells in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and sharing a match line with CAM cells in each row. The method also includes limiting a discharge voltage for the match line.

Abstract: A system and method for root booting includes a plurality of computing devices that each boot from a read-only base volume of an attached storage device that includes data common to the computing devices. The attached storage device also includes a plurality of volumes, each dedicated to one of the computing devices, which are redirect on write snapshots of the read-only base volume including unique items for the respective computing device. The read-only base volume may be stored in one or more solid state drives which may be configured as a RAID (redundant array of independent disks) and/or mirrored with one or more other storage drives. The plurality of volumes may each be stored in one or more hard disk drives which may be configured as a RAID. The attached storage device may be operable to add common data to the read-only base volume.