Abstract: Interface circuitry of a storage device or other type of processing device comprises at least one data path, and an adaptive power supply configured to provide a variable supply voltage to the data path. The adaptive power supply comprises a reference voltage circuit having a plurality of field effect transistors collectively configured to provide a variable reference voltage, with different ones of the field effect transistors being biased into different operating regions. For example, a first subset of the field effect transistors may each be biased into a linear region such that the variable reference voltage tracks variations in on-resistance of one or more corresponding field effect transistors of the data path, and a second subset of the field effect transistors may each be biased into a saturation region such that the variable reference voltage tracks variations in threshold voltage of the corresponding field effect transistors of the data path.

Abstract: The present disclosure is a system and method for improved RAID rebuilds under host IO conditions, that greatly improves rebuild times and prevents host IO starvation. A queue in a drive that is part of the RAID is used to store rebuild and host IO requests, with rebuild IOs issued to the head of the drive queue. Rebuild requests in the drive are delayed by a delay time. This delay ensures there is no unintended side effect of this invention that may result in host IO starvation for the RAID system. Delay is computed as a heuristic function from a plurality of variables, such as disk head response times, time allotted for rebuild, number of rebuild threads, drive behavior, rebuild IO profile, host IO profile including workload and locality, and a timeline of sequenced events, which in one preferred embodiment cycles every 70 seconds.

Abstract: A storage subsystem receives writes from a computer via a standard storage subsystem interface. The storage subsystem reduces a number of the writes. A single drive of the storage subsystem has primary and redundant storage devices with storage device interfaces. A disk controller of the single drive implements a data redundancy scheme by storing data associated with the reduced number of writes in the primary storage devices and by storing computed redundancy information in the redundant storage devices. The disk controller is operable without a loss of data in the presence of at least a single failure of any of the storage devices. Optionally the storage devices are flash memory devices. Optionally the disk controller is operable without a loss of data in the presence of at least two failures of any of the storage devices when a number of the redundant storage devices is at least two.

Abstract: A communication system (e.g., a hard drive) having a random-access memory (RAM) for storing trapping-set (TS) information that the communication system generates on-line during a special operating mode, in which low-density parity-check (LDPC)-encoded test codewords are written to a storage medium and then read and decoded to discover trapping sets that appear in candidate codewords produced by an LDPC decoder during decoding iterations. The discovered trapping sets are filtered to select a subset of trapping sets that satisfy specified criteria. The discovery and filtering of trapping sets is performed based on error vectors that are calculated using the a priori knowledge of original test codewords. The TS information corresponding to the selected subset is stored in the RAM and accessed as may be necessary to break the trapping sets that appear in candidate codewords produced by the LDPC decoder during normal operation of the communication system.

Abstract: Methods and apparatus are provided for approximating a probability density function or distribution for a received value in communication or storage systems. A target distribution is approximated for a received value in one or more of a communication system and a memory device, by substantially minimizing a squared error between the target distribution of the received values and a second distribution obtained by mapping a predefined distribution, such as a Gaussian distribution, through a mapping function, wherein the second distribution has an associated set of parameters. The mapping function can be, for example, a piecewise linear function. The second distribution has a plurality of segments and each of the segments has an associated set of parameters. The associated set of parameters can be used to compute probability values, soft data values or log likelihood ratios.

Abstract: An electronic device includes first and second electronic device dice. The first electronic device die is embedded within a resin layer. A dielectric layer is located over the device die and the resin layer. First interconnects within the dielectric layer connect a first subset of electrical contacts on the first electronic device to corresponding terminals at a surface of the dielectric that are located over the first electronic device. Second interconnects within the dielectric layer connect a second subset of electrical contacts on the first electronic device to corresponding bump pads at a surface of the dielectric that are located over the resin layer.

Abstract: Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.

Abstract: A method and system for parallel computation of a linear sequential circuit (LSC) based on a state transition matrix is disclosed herein. A multistep state transition matrix and a multistep output generation matrix can be pre-computed and stored in association with the linear sequential circuit. The multiple state transitions and the multiple output bits can be computed by multiplying the current input-state vector with a multistep next state transition matrix and a multistep output generation matrix, respectively. Multiple state transitions and multiple output bits can be generated in parallel in a single clock cycle based on the pre-computed state transition matrix and the output generation matrix utilizing a dot product in order to improve computational speed. Such a simple augmentation provides a flexible and inexpensive solution for high speedup linear sequential circuit computation with respect to a processor.

Abstract: A system, circuit and method for improving system-on-chip (SoC) bandwidth performance for high latency peripheral read accesses using a bridge circuit are disclosed. In one embodiment, the SoC includes the bridge circuit, one or more bus masters, at least one high bandwidth bus slave and at least one low bandwidth bus slave that are communicatively coupled via a high bandwidth bus and a low bandwidth bus. Further, the bus masters access the at least one low bandwidth bus slave by issuing an early read transaction request in advance to a scheduled read transaction request. Furthermore, the bridge circuit receives the early read transaction request and fetches data associated with the early read transaction request. In addition, the bridge circuit receives the scheduled read transaction request. The fetched data is then sent to the bus masters upon receiving the scheduled read transaction request.

Abstract: A method of sending signals, including data and timing information, between transportation units on a communication bus of an integrated circuit, by generating clock triggers for every transportation unit on the bus, thereby initiating each preceding one of the transportation units to start sending the signals in a wave-front to an adjacent succeeding one of the transportation units, where the wave-front is initiated at each of the transportation units at a common point in time, and every transportation unit applying a timing adjustment to at least one of the data and timing information that it receives in the signals from the preceding transportation unit, to at least one of (1) capture the data from the preceding transportation unit, (2) relay the data without modification from the preceding transportation unit to the succeeding transportation unit on the communication bus, and (3) load new data to the communication bus, with updated timing information in a succeeding wave-front.

Abstract: A method of detecting received data in a communication system includes the steps of: performing a QR decomposition on a received input vector as a function of one or more characteristics of a communication channel over which the input vector was transmitted; generating a subset of best symbol candidates from a symbol constellation by comparing an input sample (corresponding to an element of the input vector) with one or more prescribed thresholds; identifying at least one symbol satisfying prescribed minimum Euclidian distance criteria among multiple ambiguity symbols in the subset of best symbol candidates; and generating a subset of best symbols including a prescribed number of symbols from the symbol constellation determined to be closest to the input sample. The subset of best symbols is used in a subsequent iteration of the steps of generating the subset of best symbol candidates and identifying at least one symbol satisfying the prescribed minimum Euclidian distance criteria.

Abstract: In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile comprising a plurality of profile values. Further, an intermediate detection is performed by comparing the updated profile values to an intermediate threshold that is also updated for each chunk. Upon receiving the final chunk, the correlation profiles are updated, and a final preamble detection is made by comparing the updated profile values to a final threshold. Detections are performed on an incremental basis to meet latency requirements of the wireless network.

Abstract: Methods and devices are provided for determining compliance with standards for at least one of Serial Attached SCSI and Serial Advanced Technology Attachment (SAS/SATA). The device comprises PHY layer logic operable to couple the device with another device, and a control unit. The control unit is operable to direct operations of the PHY layer logic, and to determine that the other device is a SAS/SATA device. The control unit is further operable to perform SAS/SATA protocol compliance testing on the other device to determine a degree of compliance of the other device with SAS/SATA protocol standards, and to alter subsequent communications with the other device responsive to determining that the other device is not fully compliant with SAS/SATA protocol standards.

Abstract: A device that provides debug mode information associated with a System-on-Chip (SoC) device includes a multiplexer, debug controller, and a memory device internal to the SoC device and coupled to the multiplexer. The multiplexer directs debug mode information to the memory device in response to the SoC device being in a debug mode. The debug controller stores the debug mode information in the memory device in response to a triggering signal, and the triggering signal is associated with a triggering event. The debug controller reads data from memory device and provides the debug mode information external to the SoC device. The memory may include a first memory block and a second memory block, which store debug mode information. The first memory block may store debug mode information, and the second memory block may store normal mode information. A corresponding method and computer-readable medium are also disclosed.

Abstract: Methods and systems for updating devices of a storage system are provided. The system comprises a management system and at least one client system. The management system contacts a network-accessible portal providing updates for firmware residing on storage system devices. The client system is coupled for communication with the management system and comprises one or more storage system devices. The management system acquires version information for the storage system devices of the client system, and compares the version information for the storage system devices to version information accessible via the portal to determine whether to download updates from the portal. The client system downloads an update from the management system, determines a volume of activity at a storage system device, and pushes the update to the storage system device if the volume of activity is below a threshold.

Abstract: A transmitter comprises resource mapping circuitry configured to map symbols from multiple control channels to transmission symbols in a base station of a wireless system. The resource mapping circuitry comprises a table-based mapper configured to receive the control channel symbols and to map those symbols to the transmission symbols utilizing at least a selected one of a plurality of tables providing respective distinct mappings between the control channel symbols and the transmission symbols. For example, each of the transmission symbols may comprise a plurality of resource groups and the tables may specify distinct mappings of the control channels symbols to resource groups for different sets of possible base station parameter values. In one embodiment, the control channels comprise a physical control format indicator channel (PCFICH), a physical downlink control channel (PDCCH), and a physical hybrid ARQ indicator channel (PHICH) of an LTE cellular system.

Abstract: A lighting apparatus having a base member and a directional member are shown and described. The base member includes a first surface having a plurality of reflective elements extending therefrom. The base member also including a plurality of openings arranged in a pattern. Each openings is configured to receive a respective light source. The directional member has a portion of a reflective surface positioned relative to at least one opening to reflect light radiating from a lighting source disposed within the opening towards a portion of at least one of the reflective elements extending from the base member.

Abstract: An apparatus having a processor and a circuit is disclosed. The processor generally has a pipeline. The circuit may be configured to (i) detect a first write instruction in the pipeline that writes to a resource, (ii) stall a read instruction in the pipeline where (a) a first read-after-write conflict exists between the first write instruction and the read instruction and (b) no other write instruction to the resource is scheduled between the first write instruction and the read instruction and (iii) not stall the read instruction due to the first read-after-write conflict where a second write instruction to the resource is scheduled between the first write instruction and the read instruction.

Abstract: A path monitor, a method of monitoring a path, an integrated circuit and a library of standard logic elements. In one embodiment, the path monitor includes: (1) a delay element having an input couplable to an input of a clocked flip-flop associated with a path to be monitored and configured to provide a predetermined delay and (2) a clocked exclusive OR gate having a clock input, a first input coupled to an output of the delay element, a second input couplable to the output of the clocked flip-flop and an output at which the clocked exclusive OR gate is configured to respond to a clock signal to provide an error signal only when logic levels of the first input and the second input differ.

Abstract: A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f?n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.