Abstract: A method and storage controller for providing active-active RAID functionality within storage controller device(s). An embodiment may utilize zoning capabilities to assign a subset of physical storage devices with each storage controller. One or more storage controllers may detect that a storage controller/server has failed and may reconfigure zoning of the physical storage devices originally zoned in with the failed storage controller such that the physical storage devices of the failed zone are zoned out of the failed zone and zoned in with at least one of the remaining functional storage controllers. A reverse process may be used on recovery. An embodiment may further represent each of the physical devices zoned in with a storage controller as at least one virtual storage device and configure an additional comprehensive zone incorporating the storage controllers such that each storage controller has access to all physical storage devices through the virtual storage devices.

Abstract: A redundant array of independent disks level 5 (RAID 5) with a mirroring functionality is disclosed. In one embodiment, a method for adding a mirroring functionality to a RAID 5 includes forming an array using at least three drives for storing data, creating multiple data blocks and a parity for the multiple data blocks based on the data for every (2N?1)th stripe of the array, and generating a mirror image of the multiple data blocks and the parity for the multiple data blocks for every (2N?1)th stripe to its respective 2Nth stripe of the array, where the N is an integer starting from 1.

Abstract: A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.

Abstract: An analog-to-digital converter comprises a switched capacitor array configured to receive an analog input signal, a comparator having inputs coupled to respective outputs of the switched capacitor array, register circuitry having inputs coupled to respective outputs of the comparator, and a metastability detector associated with the register circuitry. The register circuitry is configured to generate control signals for application to respective control inputs of the switched capacitor array and to provide a digital output signal corresponding to the analog input signal. The metastability detector is configured to detect a metastability condition relating to signals at the respective outputs of the comparator. The register circuitry responsive to detection of the metastability condition forces bits of the digital output signal to particular logic levels.

Abstract: A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.

Abstract: A digital signal processing architecture supporting efficient coding of memory access information is provided. In an example embodiment, a digital signal processor includes an adjustment value register to store an initial adjustment value and a succeeding adjustment value. The digital signal processor may also include an address generator circuit to retrieve an instruction including a memory address value that is greater than N, and a further instruction including a further memory address value that is less than or equal to N. In addition, the digital signal processor may include a memory, which includes a high bank address space defined by memory locations that are uniquely identified with memory address values greater than N. The address generator circuit may access the high bank address space, using initial adjustment value and the memory address value, or using the succeeding adjustment value and the further memory address value.

Abstract: Systems and methods for performing timing sign-off of an integrated circuit design are disclosed. In one example embodiment the integrated circuit design is divided into plurality of blocks based on a pre-determined logic. A timing model is extracted for each block using static timing analysis (STA), wherein the extracted timing model includes timing information. An integrated circuit design level STA is performed using the extracted timing model of all of the plurality of blocks to obtain first integrated circuit design timing. The first integrated circuit timing is compared with a predetermined performance criterion.

Abstract: A BIIR system includes a first delay line for receiving at least one input data sample and generating delayed input samples as a function of the input data sample. The BIIR system further includes a second delay line including multiple delay elements connected in series for generating delayed output samples. An input of one of the delay elements receives at least one output data sample of the BIIR system. A summation element in the BIIR system generates the output data sample of the BIIR system as a function of an addition of at least first and second signals and a subtraction of at least a third signal. The third signal includes a first delayed output sample generated by the second delay line multiplied by a first prescribed value. The first delayed output sample and the output data sample are temporally nonadjacent to one another.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises scan delay defect bypass circuitry comprising a plurality of multiplexers arranged within said at least one scan chain. At least a given one of the multiplexers is configured to allow a corresponding one of the scan cells to be selectively bypassed in a scan shift configuration of the scan cells responsive to a delay defect associated with that scan cell. A delay defect bypass controller may be used to generate a bypass control signal for controlling the multiplexer between at least a first state in which the corresponding scan cell is not bypassed and a second state in which the corresponding scan cell is bypassed.

Abstract: A device and method wherein a thermo electric generator device is disposed between stacks of a multiple level device, or is provided on or under a die of a package and is conductively connected to the package. The thermo electric generator device is configured to generate a voltage by converting heat into electric power. The voltage which is generated by the thermo electric generator can be recycled back into the die itself, or to a higher-level unit in the system, even to a cooling fan.

Abstract: A power switch of a processing device comprises a plurality of series-connected switching stages, with each switching stage comprising a plurality of parallel-connected switching devices and an inverter chain. The switching devices are coupled between a power supply input and a power supply output of the power switch. Each of the switching devices of a given one of the switching stages is driven by an output of a corresponding one of the inverters of the inverter chain of that stage. A control input of the first switching stage receives a control signal for controlling a state of the power switch, and a control input of each remaining switching stage is driven by a control output of an immediately preceding switching stage. The switching devices in one or more of the switching stages are configured to have different switching characteristics than the switching devices in at least one other stage.

Abstract: A CAM circuit includes a plurality of core memory cells, each cell including comparison logic for generating a local match signal based on a comparison between stored data in the cell and a compare value. The CAM circuit includes a plurality of local match lines, each local match line coupled with a corresponding cell and adapted to convey the local match signal generated by the cell. The CAM circuit includes combination logic for receiving respective local match signals generated by a subset of the cells and for generating an output word match signal having a value indicative of the local match signals. The subset of cells is arranged with at least one block having a word size that is limited based on available space for routing tracks used to convey the local match signals and at least one word match signal in a base metal layer across the cells.

Abstract: A method, system, and apparatus of a vibration based user input for mobile devices are disclosed. In one embodiment, a method of controlling an electronic device includes receiving an impact signal, (e.g., a vibration generated by a user controlled impact with a surface mechanically coupled to a housing of the electronic device). The method further includes identifying a user command to the electronic device based on the impact signal, and performing a predesignated action (e.g., a mute, a power on, a power off, a volume increase, a volume decrease, a music track change, a call redirect, a call directed to voicemail, etc.) based on the user command. The user command may be identified using a number of user controlled impacts and an interval between a prior user controlled impact and a later user controlled impact.

Abstract: Various embodiments of the present invention provide systems and methods for data processing.

Abstract: A first and a second physical disk identifier, a physical Logical Block Address (LBA), a data length, and a span identifier are calculated from a data write operation. A first request command frame is created for retrieving the existing data block from the storage array, the first request command frame including at least one of the calculated parameters. At least one second request command frame is created for retrieving the at least one existing parity data block from the storage array, the at least one second request command frame including the calculated at least one second physical disk identifier and at least one of the calculated parameters. At least one new parity data block is calculated utilizing the existing data block, the new data block, and the at least one existing parity data block.

Abstract: Disclosed is a process for determining a heat index for a block of data, such as an extent, for storage tiering. Weighted scores are used for read and write operations, since solid state devices operate better with read operations than write operations. The heat index associated with each extent is a function of a base score, rather than an absolute value. The base score is determined by adding the number of extents in a hot tier plus the access score, divided by the number of extents in the hot tier. In this fashion, the base score measures the weighted I/O activity relative to the size of the hot tier.

Abstract: Contentual metadata of an extended cache is stored within the extended cache. The contentual metadata of the extended cache is approximated utilizing a counting Bloom filter. The counting Bloom filter is stored within a primary cache. Contentual metadata of the primary cache is stored within the primary cache. One of a data read or a data write is executed without accessing the contentual metadata of the extended cache stored within the extended cache.

Abstract: Methods and systems for migrating data between storage tiers may include various operations, including, but not limited to: determining at least one activity index of at least one data storage region; receiving an input/output request addressing at least one data segment included in the at least one data storage region; qualifying a data segment addressed by the input/output request for migration to at least one higher-performing storage device; and adding a data segment reference associated with a qualified data segment to a priority queue according to the at least one activity index.

Abstract: Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge, the at least one edge having one or more slots located therein. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of pairs of adjacent lead fingers extend into corresponding slots in the paddle.