Abstract: Methods and structure for directly coupling SATA hosts (SATA initiators) with SATA target devices through a SAS fabric and an enhanced SAS expander supporting such direct couplings. The enhanced SAS expander comprises SATA/STP connection logic to open a SAS (STP) connection between a directly attached SATA host and a SATA target device in response to receipt of an FIS from the host or target while no connection is presently open. The opened connection is closed after expiration of a predetermined timeout period of inactivity between the connected host and target. Thus, simpler, less costly SATA hosts and SATA target devices may be utilized while gaining the advantage of SAS architecture flexibility in configuration and scalability. SATA hosts may be coupled through the SAS fabric with a larger number of SATA target devices and multiple SATA hosts may be coupled with the SAS fabric.

Abstract: A method of designing an integrated circuit includes receiving a placement database of logic devices of an electronic device design that includes first and second logic devices. The method further includes determining a first timing window associated with a first state transition of the first logic device, and a second timing window associated with a second state transition of the second logic device. In the event that the first and second timing windows overlap, the placement database is modified, thereby reducing interaction of the first and second logic devices.

Abstract: Reframing circuitry controls communications between a physical layer device and a link layer device. In a first direction of communication, the reframing circuitry receives a container frame with the container frame having a first arrangement of columns, and outputs a virtual container frame that includes a modified version of the container frame received by the reframing circuitry, with the modified version of the container frame having a second arrangement of columns different than the first arrangement of columns. For example, the reframing circuitry in generating the modified version of the container frame may remove a path overhead column of the container frame and replace that path overhead column with a stuff column in the modified version of the container frame. The virtual container frame may be configured to include the path overhead column that was removed from the container frame in generating the modified version of the container frame.

Abstract: A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor to read data from the memory at least in part in response to a signal from first synchronizing circuitry and a signal from second synchronizing circuitry. The first synchronizing circuitry comprises a first storage element that samples a signal synchronized to the second clock signal in combination with a second storage element that samples an output of the first storage element. The first and second storage elements are triggered by inverse transitions in the first clock signal. The second synchronizing circuitry comprises third and fourth storage elements configured in a similar manner, except that they sample a signal synchronized to the first clock signal and are triggered by inverse transitions in the second clock signal.

Abstract: A timing error sampling generator, a method of performing timing tests and a library of cells are provided. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored and (2) a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level.

Abstract: An apparatus comprising an interface circuit and a controller. The interface circuit may be configured to calculate a speed signal in response to data traffic measured over a network. The controller may be configured to present and receive data from an array in response to (a) the speed signal and (b) one or more input/output requests. The interface circuit may generate the speed signal in response to a plurality of predetermined factors. The controller may present and receive the data at one of a plurality of speeds in response to the speed signal.

Abstract: A stored-pattern logic self-test system includes a memory, a device under test and a test controller. The memory stores test pattern data including test stimuli. The device under test includes a scan chain and a test access port configurable to control operation of the scan chain. The test controller is configured to test the device under test by controlling the memory to output the test stimuli to the device under test. The test controller controls the test access port to load the test stimuli into the scan chain, and receives and evaluates response data from the device under test.

Abstract: Disclosed is a method and system that adapts coefficients of taps of a Finite Impulse Response (FIR) filter to increase elimination of Inter-Symbol Interference (ISI) introduced into a digital communications signal due to distortion characteristics caused by a real-world communications channel. In the communications system there is a Finite Impulse Response (FIR) filter. The FIR filter has at least one pre and/or post cursor tap that removes pre and/or post cursor ISI from the signal, respectively. The pre/post cursor taps each have pre/post cursor coefficients, respectively, that adjusts the effect of the pre/post cursor portion of the FIR filter. The FIR filtered signal is transmitted over the channel which distorts the signal due to the changing and/or static distortion characteristics of the channel. The channel distorted signal is received at a receiver that may pass the channel distorted signal through a quantifier/decision system (e.g.

Abstract: A computer storage apparatus. In one embodiment, the apparatus includes: (1) primary file storage, (2) a controller coupled to said primary file storage and configured to provide an interface by which data is communicated therewith, (3) formula/offset file storage coupled to said controller and configured to store at least one formula/offset and (4) pointer file storage coupled to said controller and configured to store at least one pointer, said controller further configured to provide said interface based on interaction with said formula/offset file storage and said pointer file storage.

Abstract: A system and method of I/O path virtualization between a RAID controller and an environment service module (ESM) in a storage area network (SAN) is disclosed. In one embodiment, a type of I/O request is identified by an input/output (I/O) control engine upon receiving an I/O request from a host computer via a RAID controller. Further, a priority is assigned to the received I/O request based on the type of I/O request by the I/O control engine. Furthermore, the processing of the prioritized I/O request is interrupted by the I/O control engine. In addition, the prioritized I/O request is separated into a command I/O request or a status request. Also, the separated command I/O request or the status request is sent to an associated queue in a plurality of solid state drive (SSD) buffer queues (SBQ) in the I/O control engine.

Abstract: A controller is provided that receives a single enclosure management (EM) serial bit stream from an expander or other device and divides the EM serial bit stream into multiple EM serial bit streams for delivery to multiple respective midplanes or backplanes. In this way, a separate EM serial bit stream is provided to each midplane or backplane without having to increase the number of ports that are available on the expander or other device that interfaces with the backplane or midplane.

Abstract: Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words of one or more data packets. A plurality of one-port memories store the received data portions. Each one-port memory has a width W segmented into S portions of width W/S, where W/S is related to N. A second logic module provides one or more N-bit data words, from the one-port memories, corresponding to the received m N-bit data portions. In a sequence of clock cycles, the data portions are alternately transferred from corresponding segments of the one-port memories in a round-robin fashion, and, for each clock cycle, the second logic module constructs data out read from the one-port memories.

Abstract: An apparatus for monitoring at least supply voltage in an IC includes a plurality of monitor circuits distributed throughout the integrated circuit. Each of the monitor circuits is operative to receive the supply voltage, or a signal representative thereof, and to generate an output signal indicative of a comparison between the supply voltage and a reference voltage. The apparatus further includes a control circuit coupled to the plurality of monitor circuits. The control circuit is operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits.

Abstract: The present disclosure is directed to selectively protecting a portion of a track including a plurality of data sectors. The data sectors include a plurality of user sectors and one or more parity sectors. Protected bits are designated in each of the of data sectors. The protected bits are selected to have matching bit indices across the data sectors resulting in a parallel alignment of the protected bits across the user and parity sectors. One or more selections of protected bits of the user sectors are encoded across matching bit indices to generate data values in the corresponding protected bits of the parity sectors. At least one portion of at least one failed sector is recoverable by decoding at least one selection of the protected bits when a sector error occurs at a protected bit.

Abstract: Described embodiments access data in a chained, scalable storage system. A primary agent of one or more storage devices receives a host request including a logical address from a host coupled to the primary agent. The primary agent determines, based on the logical address, a corresponding physical address in at least one of the storage devices and generates, based on the physical address, a sub-request for each determined physical address in the storage devices. The primary agent sends, via a storage device interface network operable independently of the host, the sub-requests to the storage devices. The storage device interface network is a peer-to-peer network coupling the storage devices to the primary agent. The primary agent receives sub-statuses in response to the sub-requests, and determines an overall status. The primary agent provides the overall status to the host such that the host is coupled to the storage devices without a switch.

Abstract: The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.

Abstract: An apparatus includes a non-adaptive filter, an adaptive filter, and a controller. The non-adaptive filter may have non-adaptive filter coefficients and be configured to develop a non-adaptive error signal as a function of the non-adaptive filter coefficients. The adaptive filter may have adaptive filter coefficients and be configured to develop an adaptive error signal as a function of the adaptive filter coefficients. The controller may be configured to monitor a quality of the non-adaptive and adaptive error signals and perform one or more of a full coefficient update, a partial coefficient update and a fractional coefficient update of the non-adaptive filter coefficients based on a comparison of the quality of the adaptive error signal to a determined current best-attained performance measurement.

Abstract: A multiplier circuit for generating a product of at least first and second multiplicands includes encoding circuitry comprising a plurality of encoders. Each of the encoders is operative to receive at least a subset of bits of the first multiplicand and to generate a partial product corresponding to the subset of bits of the first multiplicand. The encoding circuitry is further operative to incorporate a negation of the product as a function of at least a first control signal supplied to the multiplier circuit. The multiplier circuit further includes summation circuitry coupled with the encoding circuitry. The summation circuitry is operative to sum each of the partial products generated by the encoding circuitry to thereby generate the product without performing post-incrementation.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: A memory circuit includes a memory including a plurality of primary memory elements, and an error correction circuit coupled to the memory and operative to detect an error in at least one of the primary memory elements and to provide corrected data corresponding to the primary memory element. The memory circuit further includes at least one spare memory element and a control circuit operative to replace at least one of the primary memory elements with the spare memory element as a function of results generated by the error correction circuit.