Abstract: A method and system for reducing head related transfer function (HRTF) storage requirements for 3-D sound processing of an input sound having a specified source angle increment is provided. Interaural time difference (ITD) values are selected based directly on the source angle increment; and HRTFs for processing the input sound are stored in angle increments larger than the source angle increment.

Abstract: A method and apparatus generating one or more clock signals in a receiver employing decision-feedback equalization (DFE). A received signal is sampled by a data clock and a transition clock, generating a data sample signal and a transition sample signal, respectively. A DFE correction is performed by DFE circuitry on the data sample signal to generate DFE detected data bits. The transition sample signal is sliced using a weighted threshold value to generate transition data bits. One or more phase updates of the data clock and the transition clocks are in response to the DFE detected data bits and the transition data bits. The weighted threshold is calculated from at least one of the prior-received DFE detected data bits. In one embodiment, the DFE detection may also be dependent on an effective delay (?) of the DFE circuit in relation to the received signal baud-period, T.

Abstract: Methods and apparatus are provided for processing a signal in a read channel using an oversampled analog to digital conversion. An oversampled analog to digital conversion is performed on an analog input signal to generate a plurality of digital samples corresponding to the analog input signal for a given bit interval. A data detection algorithm can then be applied on one or more of the digital samples to obtain a detected output. The oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain.

Abstract: Disclosed is a virtual machine system where hardware timer interrupts are processed by a first virtual machine. The first virtual machine writes a timer value to a shared memory location while processing the hardware timer interrupt. The timer value may be based on a kernel timing parameter maintained by the operating system of the first virtual machine. A second virtual machine may read the shared timer value from the shared memory location in order to time inter-virtual machine processes such as I/O processing and I/O requests.

Abstract: In one embodiment, a reconfigurable cyclic shifter is selectively configurable to operate in (i) five-bit mode to cyclically shift N five-bit messages by up to N degrees or (ii) ten-bit mode to cyclically shift N ten-bit messages by up to N degrees. The reconfigurable cyclic shifter has two five-bit N/2-way non-reconfigurable cyclic shifters. The two non-reconfigurable cyclic shifters together, without additional hardware, do not perform N degrees of cyclic shifting. Thus, five-bit and ten-bit reordering hardware is provided that enables the reconfigurable cyclic shifter to perform up to N degrees of cyclic shifting in the five- and ten-bit modes, respectively. In the five-bit mode, the N five-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts N/2 of the N messages. In ten-bit mode, N/2 of the N ten-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts five of the ten bits of each ten-bit message.

Abstract: Various embodiments of the present invention provide systems and methods for variable iteration data processing.

Abstract: A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.

Abstract: A system for, and method of, reducing IC timing derating for a path in an integrated circuit design. In one embodiment, the system includes an electronic design automation tool configured to (1) extract circuit data regarding cells in the path and (2) calculate a timing derating for the path based at least in part on a determination as to whether the cells are simple cells.

Abstract: Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.

Abstract: A computer-readable medium, a method of conducting a video game and a gaming system. In one embodiment, the medium contains programming instructions that cause a computer processor to: (1) conduct a video game that generates events having corresponding exclusively audible prompts and (2) convey the exclusively audible prompts to specific audio channels for sound-capable gaming controllers of a gaming system.

Abstract: A contact event between a sensing device and a storage medium is detected by receiving a signal indicating a physical proximity between the sensing device and the storage medium; generating a plurality of frequency bin outputs; comparing one or more frequency bin outputs to a corresponding first level threshold to yield a corresponding comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; comparing the aggregated value to an aggregate threshold to yield an aggregate output; and generating a contact event output if one or more of a first group of the plurality of frequency bin outputs has an associated aggregate output set to a predefined binary value and a predefined minimum number of a second group of the plurality of frequency bin outputs has an associated aggregate output set to a predefined binary value.

Abstract: A system and method for handling IO to drives in a RAID system is described. In one embodiment, the method includes providing a multiple disk system with a predefined strip size. IO request with a logical block address is received for execution on the multiple disk system. A plurality of sub-IO requests with a sub-strip size is generated, where the sub-strip size is smaller than the strip size. The generated sub-IO commands are executed on the multiple disk system. In one embodiment, a cache line size substantially equal to the sub-strip size is assigned to process the IO request.

Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: Techniques are disclosed for canceling an offset component (e.g., dc component or dc offset) in an amplifier circuit. For example, an apparatus comprises an amplifier circuit with an amplifier element and a feedback resistor network coupled between an output of the amplifier element and an input of the amplifier element. The apparatus also comprises a current source coupled to the feedback resistor network, the current source generating a current signal that generates a voltage in a first portion of the feedback resistor network that cancels an offset component present in an input signal received by the amplifier circuit. A second portion of the feedback resistor network may be adjustable so that a gain applied to the input signal is adjustable while the offset component is canceled from the input signal. One or more resistors in the feedback resistor network may be composed of the same or substantially similar material as one or more resistors associated with the current source.

Abstract: A method and controller device for supplying battery power to a virtualized storage environment having a storage controller with a virtual machine manager and a second virtual machine. In response to a battery engaged event, the first virtual machine manager enables the image of the second virtual machine to be shared with a new instance of the second virtual machine so that the image does not have to be loaded therein. The first virtual machine manager then creates the new virtual machine. The old virtual machine shuts down non-necessary hardware devices and sets necessary hardware devices to low power mode. During this time, the new virtual machine executes a backup specific start-of-day (SOD) initialization sequence. The method also synchronizes the new and old virtual machines. The method also initiates a cache memory backup operation upon synchronization of the new and old virtual machines and then shuts down the old virtual machine.

Abstract: Methods and apparatus are provided for read-side intercell interference mitigation in flash memories. A flash memory device is read by obtaining a read value for at least one target cell; obtaining a value representing a voltage stored in at least one aggressor cell that was programmed after the target cell; determining intercell interference for the target cell from the at least one aggressor cell; and obtaining a new read value that compensates for the intercell interference by removing the determined intercell interference from the read value for the at least one target cell. The new read value can optionally be provided to a decoder. In an iterative implementation, one or more intercell interference mitigation parameters can be adjusted if a decoding error occurs.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values. The delay stage includes M parallel-coupled inverter stages. Each parallel-coupled inverter stage includes N pairs of stacked PMOS transistors and stacked NMOS transistors. The N transistor pairs have configurable source-drain node connections between a drain node and a source node of each transistor in the pair, wherein the selectable delay value corresponds to a configuration of the configurable source-drain node connections to adjust a delay value of each of the M inverter stages.

Abstract: In one embodiment, an LDPC decoder attempts to recover an originally-encoded LDPC codeword based on a set of channel soft-output values. If the decoder observes a trapping set, then the decoder compares the observed trapping set to known trapping sets stored in a trapping-set database to determine whether or not the observed trapping set is a known trapping set. If the observed trapping set is not known, then the decoder selects a most-dominant trapping set from the trapping-set database and identifies the locations of erroneous bit nodes in the selected trapping set. Then, the decoder adjusts the channel soft-output values corresponding to the identified erroneous bit nodes. Adjustment is performed by inverting some or all of the hard-decision bits of the corresponding channel soft-output values and setting the confidence value of each corresponding channel soft-output value to maximum. Decoding is then restarted using the adjusted channel soft-output values.

Abstract: An electronic design automation (EDA) tool and a method of employing unsensitized critical path information to reduce leakage power in a circuit. In one embodiment, the EDA tool includes: (1) an unsensitizable path identifier configured to receive information regarding designed devices in a circuit and information regarding identified critical paths therein, analyze a logical behavior of the circuit and identify critical and noncritical gates in unsensitizable ones of the critical paths thereof and (2) a transistor designator coupled to the unsensitizable path identifier and configured to designate relatively low threshold voltage transistors for use in the critical gates and designate relatively high threshold voltage transistors for use in the noncritical gates.

Abstract: In one embodiment, an LDPC decoder has a controller and an extrinsic log-likelihood (LLR) value generator. The extrinsic LLR value generator is selectively configurable to operate in either (i) a non-averaging mode that updates extrinsic LLR values without averaging or (ii) an averaging mode that updates extrinsic LLR values using averaging. Initially, the extrinsic LLR value generator is configured to generate non-averaged extrinsic LLR values, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged extrinsic LLR values. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) the extrinsic LLR value generator is configured to generate average extrinsic LLR values, and (iii) the decoder attempts to recover the correct codeword using the average extrinsic LLR values. Averaging the extrinsic LLR values may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.