Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, an inter-track interference signal estimator circuit, and a sync mark detector circuit. The data buffer is operable to store a previous track data set that includes a first sync pattern. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The current track data set includes a second sync pattern. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes providing a decoder processing circuit having a first memory, a second memory, and a decoder circuit; and providing a centralized queue communicably coupled to the decoder processing circuit. A first data set is loaded from the centralized queue to the first memory, and concurrent with the loading the first data set, a data decoding algorithm is applied to a second data set by the decoder circuit.

Abstract: An apparatus generally having a lookup table and a circuit is disclosed. The lookup table may be configured to store a plurality of results including remainders of divisions by a particular polynomial. The circuit may be configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from the lookup table by indexing the lookup table with each of the data blocks and (iii) generate a second polynomial by adding the results fetched from the lookup table to the end block. The second polynomial generally has a second degree that is lower that a first degree of the first polynomial.

Abstract: Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location.

Abstract: Apparatus and methods improved fair access to a Fiber Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.

Abstract: A computing system peripheral device compatible with the peripheral component interconnect express (PCI-E) protocol responds to a DL_DOWN command primitive by configuring a general-purpose input/output (GPIO) port into a known state without invoking a GPIO module reset. In addition, select resources are excluded from resources on the peripheral device that are issued a reset command. The select resources can include a GPIO module, a memory element and a PCI-E SERDES module. After the remaining reset resources have completed their individual initialization processes, the central processor core on the peripheral device is reset. The described response to the DL_DOWN command primitive avoids cache data loss, masks signal transitions on I/O ports and timing problems that prevent some peripheral devices from being recognized in a computer's basic input/output system (BIOS).

Abstract: The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and also determining a reclaimed space, the reclaimed space being according to a difference between the size of the data received from the host and the compressed data size. The system may also include an interface module for presenting a logical capacity to the host. The logical capacity has a variable size and may include at least a portion of the reclaimed space.

Abstract: In certain embodiments, a slave clock node in a wireless packet network achieves time synchronization with a master clock node by implementing a packet-layer synchronization procedure, such as the IEEE1588 precision timing protocol (PTP), to set the slave's local time based on the master's time. The slave's local time is then maintained by implementing a physical-layer syntonization procedure, such as synchronous Ethernet, without relying on the packet-layer synchronization procedure. The packet-layer synchronization procedure may be selectively employed to adjust the slave's local time (if needed) after significant periods of time (e.g., substantially greater than one second). Both the packet-layer synchronization procedure and the physical-layer syntonization procedure are traceable to a common reference timescale (e.g., UTC). Depending on the implementation, the packet-layer synchronization procedure can be, but does not have to be, terminated when not being employed to adjust the slave's local time.

Abstract: Described embodiments provide for a semiconductor device comprising a core and one or more input/output (I/O) buffers surrounding the core. The I/O buffers are adapted to transfer signals associated with core circuitry of the core. The I/O buffers comprise I/O cells having a first orientation and I/O cells having a second orientation. Each I/O cell has a corresponding translator having low voltage transistors in a corresponding footprint. The low voltage transistors in the first orientation I/O cells have the first orientation, and the low voltage transistors in the second orientation I/O cells have the first orientation. The footprints of the first orientation I/O cells and the second orientation I/O cells are compatible with one another.

Abstract: A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array.

Abstract: The present invention is directed to a method for providing storage acceleration in a data storage system. In the data storage system described herein, multiple independent controllers may be utilized, such that a first storage controller may be connected to a first storage tier (ex.—a fast tier) which includes a solid-state drive, while a second storage controller may be connected to a second storage tier (ex.—a slower tier) which includes a hard disk drive. The accelerator functionality may be split between the host of the system and the first storage controller of the system (ex.—some of the accelerator functionality may be offloaded to the first storage controller) for promoting improved storage acceleration performance within the system.

Abstract: A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding data in a RAID system includes rebuilding the data from parity information and storing the rebuilt data on reserve portions of the remaining disks in the system.

Abstract: A method of designing a model of an integrated circuit block, an electronic design automation tool and a non-transitory computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating an input and output timing budget for the block based on design constraints of the block and a netlist of the block, (2) updating the input and output timing budget with clock customization data based on designer knowledge of the integrated circuit and (3) providing the model for the block based on the update of the input and output timing budget, wherein the model represents clock information of the block separately from data path information of the block.

Abstract: In one embodiment of a header-compression method, a timestamp value is divided by a stride value using a plurality of binary-shift operations corresponding to a Taylor expansion series of the reciprocal stride value in a base of ½. When the division-logic circuitry of an arithmetic logic unit in the corresponding communication device is not designed to handle operands that can accommodate the length of the timestamp and/or stride values, the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.

Abstract: A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.

Abstract: A search method for identifying an intra mode that can produce acceptable video-encoding quality for a pixel block while striking a proper balance between the quality and processor load. In a representative embodiment, the search method relies on a set of mode-selection rules for iteratively identifying candidate intra modes. Each identified candidate is evaluated based on a comparison of its sum of absolute differences (SAD) with the smallest SAD in the set of the previously identified candidates. The mode-selection rules use the comparison results as conditions that efficiently guide the search method toward an intra mode that is suitable for encoding the pixel block with acceptable video quality. On average, a representative embodiment of the search method disclosed herein is advantageously capable of finding a suitable intra mode in fewer iterations than a comparable prior-art search method.

Abstract: In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may (i) generate a decoded codeword by decoding a first codeword a plurality of times based on a respective plurality of erasure location vectors and (ii) assert a fail signal upon each failure of the decoding of the first codeword, the decoding comprising an error-and-erasure Reed-Solomon decoding. The second circuit may (i) generate a count of the assertions of the fail signal and (ii) generate the erasure location vectors based on (a) the count and (b) a plurality of reliability items corresponding to the first codeword.