Abstract: A method for reducing a timing violation in a negative slack path from an integrated circuit design, by identifying the negative slack path in the integrated circuit design with a processor, and then identifying positive slack paths by determining timing slack for the paths that are disposed before and after the negative slack path. A prediction is made as to whether margin can be obtained from the positive slack paths by performing additional timing optimization on the positive slack paths, and it is determined whether that margin is sufficient to reduce the timing violation to at least a desired level. If the margin is sufficient, then additional timing optimization is performed on the positive slack paths, and the margin is used to manipulate the clock skew and reduce the timing violation on the negative slack path.

Abstract: Methods operable on a storage controller and related structure are provided for responding to inquiry commands from a host for a storage device. A command requesting information about a storage device is received from a host. In response to the command, the storage controller determines that the storage device is not initialized, and begins an initialization process for the storage device. Information received from the storage device during the initialization process is stored for completing a response to the inquiry. A response to the inquiry is transmitted to the host based on the stored information to complete the inquiry without waiting for the storage device to complete the initialization.

Abstract: The present invention is directed to a method for implementing firmware in an expander system in such a way that a single hardware component (ex.—a chip) of the expander system may be presented as multiple virtual expanders to both upstream connected devices (ex.—HBAs) as well as downstream connected devices (ex.—disk drives).

Abstract: Devices and systems for tool-less assembly of cable chains that are capable of being retractably stored. The device comprises a first contact element, a second contact element, and a lengthwise member. The first contact element is adapted for movable contact with a receiving member of a first cable chain segment. The second contact element is adapted for movable contact with a receiving member of a second cable chain segment. The lengthwise member is fixedly attached to the contact elements. When an angle between the first and the second cable chain segments is a first value, the lengthwise member experiences elastic deformation, generating a spring force at each contact element sufficient to pull the receiving member of the first cable chain segment rotatably towards the receiving member of the second cable chain segment, thereby reducing the angle between the first and the second cable chain segments to a second value.

Abstract: Apparatus and methods for improved high-speed communication by exchanging low-speed information regarding the high-speed exchanges over the same communication medium. In one exemplary embodiment, a communication device includes a high-speed transceiver adapted to exchange high-speed data with another device via a communication medium using high-frequency signals. The device also includes a low-speed component adapted to exchange low-speed information over the same communication medium as low-frequency signals. The low-frequency signals may be applied as common mode signals to a differential communication path so as to not interfere with the high-speed data exchanges. In another embodiment, a high-pass filter may be included in the device to remove the low-frequency signals before the high-speed data is applied to the high-speed transceiver. Responsive to receipt of the low-speed information, a device may adjust parameters of the transceiver to improve the high-speed data exchanges.

Abstract: The present disclosure provides testing of a storage system. The test may compare the storage array controller LUNs which may be configured to be accessible by a host with the LUNs which are currently available to prevent a zero path scenario from occurring. The test may verify at least one path exists for each LUN to a storage controller of a storage array before injecting an error into another storage controller of the storage array. The present disclosure also provides verification of the configuration of a storage system. The configuration verification may verify that the storage array controller LUNs which are configured to be accessible by a host are actually accessible by the host. If the configuration verification is unable to verify the configuration of storage system, the configuration verification may display an error.

Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.

Abstract: An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit.

Abstract: A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.

Abstract: An apparatus generally having a processor and a direct memory access controller is disclosed. The processor may be configured to increment a task counter to indicate that a new one of a plurality of tasks is scheduled. The direct memory access controller may be configured to (i) execute the new task to transfer data between a plurality of memory locations in response to the task counter being incremented and (ii) decrement the task counter in response to the executing of the new task.

Abstract: A method for composite noise filtering is disclosed. The method generally includes the steps of (A) generating a selection value in response to a stationary check identifying one of a plurality of blendings for a current item of a current field, (B) generating a filtered item in response to one of (i) a first of the blendings between the current item and a first previous item co-located in a first previous field having an opposite phase of composite artifacts from the current field and (ii) a second of the blendings between the current item and a first motion compensated item from the first previous field and (C) switching between the first blending and the second blending in response to the selection value.

Abstract: Embodiments of the invention include a method for modifying firmware settings within a data storage controller, such as a data storage controller used in a Redundant Array of Inexpensive Disks (RAID) storage array. The method includes extracting a sub-module from a firmware image stored in the controller, stripping off the sub-module's header, decompressing the remaining compressed image by replacing the stripped sub-module header and an extended image header in the compressed image with an extended header image that allows conventional decompression, and separating the decompressed image into its executable code and at least one settings group.

Abstract: The present invention is directed to an information handling system device for operatively coupling with a device implementing Input/Output (I/O) virtualization for data transmission. The information handling system device may be configured for executing an operating system control program to manage one or more guest operating systems on the information handling system device. The operating system control program may include a paravirtualization driver for formulating a work queue entry according to the I/O virtualization of the device. Data may be transmitted between the one or more guest operating systems and the device via the paravirtualization driver.

Abstract: Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

Abstract: Various embodiments of the present invention provide systems and methods for servo data based harmonics calculation. For example, a circuit for determining harmonics is disclosed that includes an analog to digital conversion circuit that provides a series of digital samples corresponding to a pattern within a servo data region of a storage medium, and a harmonic calculation circuit. The harmonic calculation circuit is operable to calculate a first harmonic value for the series of digital samples, calculate a second harmonic value for the series of digital samples, and calculate a ratio of the first harmonic value to the second harmonic value.

Abstract: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier circuit, an analog to digital conversion circuit, a cosine component calculation circuit, a sine calculation circuit, and a zero gain start calculation circuit. The variable gain amplifier circuit is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The analog to digital conversion circuit is operable to convert the amplified output to a corresponding series of digital samples. The cosine component calculation circuit is operable to calculate a cosine component from the series of digital samples, and the sine component calculation circuit operable to calculate a sine component from the series of digital samples.

Abstract: A method and system for eliminating implementation timing with respect to a synchronization circuit. A standard library cell having a pair of clock input pins can be connected with at least two asynchronous clock domains of the synchronization circuit in order to measure a timing signal between the flip-flop latches crossing the asynchronous clock domain. A timing delay with respect to each bit pair of the asynchronous clock domain can be determined utilizing a static analysis approach during a layout phase in order to effectively synchronize the asynchronous clock domain. Each bit pair of the asynchronous clock domain can be checked via a static timing analysis tool in order to thereby improve functional accuracy of the synchronization circuit in a wide range of digital logic designs.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate an equalized signal in response to an input signal and an equalizer parameter signal. The equalizer parameter signal generally causes a cancellation of pre-cursor inter-symbol interference from a plurality of symbols in the input signal. The second circuit may be configured to generate (i) the equalizer parameter signal, (ii) a control signal and (iii) a data output signal in response to the equalized signal. The control signal generally causes an adjustment of the equalizer parameter signal. The adjustment of the equalizer parameter signal generally causes a decrease in the pre-cursor inter-symbol interference from the symbols.

Abstract: In one embodiment, an LDPC decoder has one or more reconfigurable adders that generate variable-node messages and one or more reconfigurable check-node units (CNUs) that generate check-node messages. The LDPC decoder has a five-bit precision mode in which the reconfigurable adders and CNUs are configured to process five-bit variable-node and check-node messages, respectively. If the LDPC decoder is unable to properly decode codewords in five-bit precision mode, then the decoder can be reconfigured in real time into a ten-bit precision mode in which the reconfigurable adders and CNUs are configured to process ten-bit variable-node and check-node messages, respectively. By increasing the size of the variable-node and check-node messages from five bits to ten bits, the probability that the LDPC decoder will decode the codeword correctly may be increased.