Abstract: methods and systems for monitoring data activity may include various operations, including, but not limited to: modifying a value of at least one counter in response to one or more input/output requests directed to at least one data storage region during a first time interval; storing a first cumulative value of the counter modified in response to one or more input/output requests directed to at least one data storage region during the first time interval following the expiration of the first time interval; modifying a value of at least one counter in response to one or more requests directed to the at least one data storage region during a second time interval; storing a second cumulative value of the counter modified in response to one or more requests directed to the at least one data storage region during the second time interval following the expiration of the second time interval; and computing at least one activity index for the at least one data storage region from at least the first cumulative value

Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.

Abstract: A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively.

Abstract: Methods and systems for improved update of firmware for components in a storage system/network. A storage network comprising one or more initiator components coupled through one or more switching components to one or more target components may be updated by generating and distributing a package buffer comprising portions where each portion comprises firmware for a corresponding type of component. Switching and/or initiator components in the system locate a portion of the package buffer for each target component directly coupled to it and transmits the located, corresponding portion (comprising firmware) to each target component. Each initiator/switching component then also forwards the entire package buffer to each other switching component coupled with it and the process repeats until all components have received updated firmware.

Abstract: In one embodiment, a network processor services a plurality of queues having data using weighted round robin scheduling. Each queue is assigned an initial weight based on the queue's priority. During each cycle, an updated weight is generated for each queue by adding the corresponding initial weight to a corresponding previously generated decremented weight. Further, each queue outputs as many packets as it can without exceeding its updated weight. As each packet gets transmitted, the updated weight is decremented based on the number of blocks in that packet. If, after those packets are transmitted, the decremented weight is still positive and the queue still has data, then one more packet is transmitted, no matter how many blocks are in the packet. When a decremented weight becomes negative, the weights of the remaining queues are increased to restore the priorities of the queues as set by the initial weights.

Abstract: A uterine manipulator includes a sound and a body. The sound has a selectively actuatable anchor disposed proximate a distal end and an operating mechanism spaced from the anchor for controlling actuation of the anchor. The body has a passage therethrough adapted to receive the sound passed proximally through the body to a position in which the operating mechanism is accessible proximally of the body and the anchor extends distally.

Abstract: A method for metadata management in a storage system may include providing a metadata queue of a maximum size; determining whether the metadata for a particular sub-LUN is held in the metadata queue; updating the metadata for the particular sub-LUN when the metadata for the particular sub-LUN is held in the metadata queue; inserting the metadata for the particular sub-LUN at the head of the metadata queue when the metadata queue is not full and the metadata is not held in the metadata queue; replacing an entry in the metadata queue with the metadata for the particular sub-LUN and moving the metadata to the head of the metadata queue when the metadata queue is full and the metadata is not held in the metadata queue; and controlling the number of sub-LUNs in the storage system to manage data accessed with respect to an amount of available data storage.

Abstract: The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal via the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.

Abstract: The present disclosure is directed to a system and a method for optimizing redundancy restoration in distributed data layout environments. The system may include a plurality of storage devices configured for providing data storage. The system may include a prioritization module communicatively coupled to the plurality of storage devices. The prioritization module may be configured for determining a restoration order of at least a first data portion and a second data portion when a critical data failure occurs. The system may include a restoration module communicatively coupled to the plurality of storage devices and the prioritization module, the restoration module configured for restoring at least the first data portion and the second data portion based upon the restoration order.

Abstract: A method and systems of adaptation of an active power supply set using an event trigger are disclosed. In an embodiment, a method includes providing power to a system load using an active power supply set. The active power supply set includes a power supply in an active mode. The method also includes detecting an event trigger. In addition, the method includes increasing a power mode of an additional power supply when the event trigger is detected. The method may include detecting an additional event trigger and decreasing the power mode of a unit of the active power supply set when the additional event trigger is detected.

Abstract: The present disclosure describes a system and method for allocating volume pieces across a redundant array of inexpensive discs (RAID). A method for allocating volume pieces across a redundant array of inexpensive discs (RAID) may comprise: (a) associating one or more volume pieces of a first logical volume with a first set of drives in a drive group; and (b) associating one or more volume pieces of a second logical volume with a second set of drives in the drive group, wherein the first set of drives in the drive group includes at least one drive which is not a member of the second set of drives in the drive group.

Abstract: A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.

Abstract: Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

Abstract: An apparatus comprising a plurality of buffers and a memory controller. The plurality of buffers may each be configured to generate an access request signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The memory controller circuit may be configured to generate a clock enable signal in response to the plurality of access request signals. The clock enable signal may be configured to initiate entering and exiting a power savings mode of a memory circuit.

Abstract: An apparatus comprising a write data buffer circuit, a memory, and a read data buffer circuit. The write data circuit may be configured to present data in a second format in response to data received in a first format. The memory may be configured to (i) receive the data in the second format and (ii) present the data in the second format. The read data buffer circuit may be configured to (i) receive data in the second format and (ii) present data in a third format. The memory may be configured to allow two reads or two writes during a single clock cycle of reference clock without encountering a data overflow condition.

Abstract: A method of generating a motion menu in a low memory environment. The method generally includes the steps of (A) generating a plurality of encoded streams in a buffer by encoding a fixed duration from each of a plurality of title streams received in a video program, (B) generating a plurality of thumbnails frames in the buffer by decoding each of the encoded streams and (C) generating the motion menu in the buffer by combining one of the thumbnail frames from each respective one of the encoded streams into a respective one of plurality of menu frames such that a sequential display the menu frames appears as a plurality of thumbnails having dynamic content in the motion menu.

Abstract: An apparatus for performing data caching comprises at least one cache memory including multiple cache lines arranged into multiple segments, each segment having a subset of the cache lines associated therewith. The apparatus further includes a first plurality of counters, each of the counters being operative to track a number of active cache lines associated with a corresponding one of the segments. At least one controller included in the apparatus is operative to receive information relating to the number of active cache lines associated with a corresponding segment from the first plurality of counters and to implement a cache segment replacement policy for determining which of the segments to replace as a function of at least the information relating to the number of active cache lines associated with a corresponding segment.

Abstract: An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals.

Abstract: A global power distribution network in an integrated circuit comprising a first layer of conductive material and a second layer of conductive material. The first layer of conductive material may be (i) coupled to one or more power supplies and (ii) configured to form a plurality of first rails of a mesh. The first rails may (a) supply power to one or more components of a core logic of the integrated circuit, (b) be aligned with a first axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh has a uniform voltage gradient from a perimeter of the integrated circuit to a center of the integrated circuit along the first axis. The second layer of conductive material may be (i) coupled to the one or more power supplies and (ii) configured to form a plurality of second rails of the mesh.

Abstract: An electronic device package 100 comprising a lead frame 150 having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.