Abstract: A lighted architectural mesh includes a plurality of interconnected wires forming a plurality of transverse openings. At least one light carrier is slidably received within at least one of said transverse openings. The at least one light carrier includes light nodes emitting light through the interstices on the front and/or rear side of the architectural mesh. The at least one light carrier further comprises a plurality of connecting elements, wherein the light emitter nodes of the at least one light element are releasably interconnected in series by the connecting elements.

Abstract: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

Abstract: A method for correcting at least one error in a data transmission over a packet-based communication network includes the steps of: generating a sequence of data packets for transmission over the packet-based communication network, the sequence of data packets being arranged into a plurality of packet frames, each of at least a subset of the packet frames including at least a primary data packet and a number of redundant data packets which is a function of a prescribed redundancy pattern, the subset of packet frames having a non-uniform distribution of redundant data packets therein; transmitting the sequence of data packets over the communication network; and recovering at least one missing data packet in the sequence of data packets using at least one corresponding redundant data packet in at least one subsequently received packet frame when the missing data packet is identified in a receiver of the sequence of data packets.

Abstract: Methods and circuits in an application circuit to compensate for skew in the transmission of serial data between field programmable gate arrays (FPGAs) in the application circuit. A clock signal source external to both FPGAs generates a clock signal applied to both FPGAs. A transmitting FPGA generates a serial data stream comprising the current values of a plurality of signals within the transmitting FPGA and transmits the serial data stream based on its clock signal. The receiving FPGA receives the serial data stream and applies a programmed delay to the received serial data stream to compensate for skew in received serial data stream relative to its clock signal. The programmed delay value may be determined at initialization (or reset) of the FPGAs by transmitting synchronization data from the first transmitting FPGA to the receiving FPGA. The receiving FPGA adjusts a programmable delay while receiving synchronization data until it sense bit and word alignment relative to its clock signal.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.

Abstract: A method for dynamic storage tiering may include, but is not limited to: receiving an input/output (I/O) request from a host device; determining whether the I/O request results in a cache hit; and relocating data associated with the I/O request between a higher-performance storage device and lower-performance storage device according to the determination whether the data associated with the I/O request is stored in a cache.

Abstract: An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.

Abstract: A circuit for use with a memory storage device including a magnetic storage medium and a write head operative to subject the magnetic storage medium to a magnetic field in response to an application of current to the write head, includes a write circuit operative to generate a write current supplied to the write head. The write current is characterized by a current waveform that reverses polarity in accordance with data to be stored on the magnetic medium. The circuit for use with the memory storage device further includes a degauss circuit operative to generate a degaussing current supplied to the write head. The degaussing current is characterized by a current waveform that oscillates between opposite polarities with an amplitude and a frequency that change over time.

Abstract: In one embodiment, a forward substitution component performs forward substitution based on a lower-triangular matrix and an input vector to generate an output vector. The forward substitution component has memory, a first permuter, an XOR gate array, and a second permuter. The memory stores output sub-vectors of the output vector. The first permuter permutates one or more previously generated output sub-vectors stored in the memory based on one or more permutation coefficients corresponding to a current block row of the lower-triangular matrix to generate one or more permuted sub-vectors. The XOR gate array performs exclusive disjunction on (i) the one or more permuted sub-vectors and (ii) a current input sub-vector of the input vector to generate an intermediate sub-vector. The second permuter permutates the intermediate sub-vector based on a permutation coefficient corresponding to another block in the current block row to generate a current output sub-vector of the output vector.

Abstract: The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.

Abstract: Described embodiments provide a network processor that includes a security protocol processor for staged security processing of a packet having a security association (SA). An SA request module computes an address for the SA. The SA is fetched to a local memory. An SA prefetch control word (SPCW) is read from the SA in the local memory. The SPCW identifies one or more regions of the SA and the associated stages for the one or more regions. An SPCW parser generates one or more stage SPCWs (SSPCWs) from the SPCW. Each of the SSPCWs is stored in a corresponding SSPCW register. A prefetch module services each SSPCW register in accordance with a predefined algorithm. The prefetch module fetches a requested SA region and provides the requested SA region to a corresponding stage for the staged security processing of an associated portion of the packet.

Abstract: A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal.

Abstract: The present disclosure describes systems and methods for arbitrating between a plurality of devices competing for a system resource. Operations of the system and method may include, but are not limited to: initializing two or more previous grant request states; generating an access grant signal according to the two or more requests for access to the shared resource, two or more token states and the two or more previous grant request states; and generating an access grant signal according to the two or more requests for access to the shared resource, two or more token states and the two or more previous grant request states.

Abstract: Methods and systems for improving performance in a storage system utilizing snapshots are disclosed by using metadata management of snapshot data. Specifically, various metadata structures associated with snapshots are utilized to reduce the number of IO operations required to locate data within any specific snapshot. The number of IO operations are reduced by allowing the various metadata structures associated with the temporally current snapshot to locate data directly within any temporally earlier snapshot or on the original root volume.

Abstract: A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.

Abstract: A method for correcting signals received on a channel. Signals are received along the channel and it is determined how many of the signals are outside a predetermined range relative to a plurality of predetermined constellation points (i.e., erasures). Then, the noise power is estimated the noise power based on the number erasures, and the noise power is used to correct the signals. Specifically, the estimated noise power can be used to correct the signals which have been determined to be outside the predetermined range and which have been determined to contain a large error component (i.e., based on distance from the closest constellation point). A look up table can be used to determine the correction to be applied, and a separate look up table can be used for each tone.

Abstract: A method for reducing noise in an output of a voltage regulator at frequencies above a closed loop bandwidth, by providing a noise injection path for injecting external noise into the voltage regulator, where the noise injection path becomes active at the frequencies above the closed loop bandwidth, where the noise injection path reduces the noise in the output of the voltage regulator.

Abstract: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.

Abstract: A processor (e.g., a Digital Signal Processor (DSP) core) rewinds a pipeline of instructions upon a watchpoint event in an instruction being processed. The program execution ceases at the instruction in which the watchpoint event occurred, while the instruction and subsequent instructions are cancelled, keeping the hardware components associated with executing the program in their previous states, prior to the watchpoint. The rewind is such that the program is refetched to enable execution to continue from the instruction in which the watchpoint event occurred. The watchpoint event is executed in a “break before make” manner.