Abstract: Described embodiments provide for transfer of data between data modules. At least two crossbar switches are employed, where input nodes and output nodes of each crossbar switch are coupled to corresponding data modules. The ith crossbar switch has an Ni-input by Mi-output switch fabric, wherein Ni and Mi are positive integers greater than one. Each crossbar switch includes an input buffer at each input node, a crosspoint buffer at each crosspoint of the switch fabric, and an output buffer at each output node. The input buffer has an arbiter that reads data packets from the input buffer according to a first scheduling algorithm. An arbiter reads data packets from a crosspoint buffer queue according to a second scheduling algorithm. The output node receives segments of data packets provided from one or more corresponding crosspoint buffers.

Abstract: Described embodiments provide a method of allocating resources of a media controller for a data transfer. A data transfer request is received from at least one host device, and includes a host device ID and a data transfer request ID. The media controller generates a Tag ID of the data transfer request based on the host device ID and the data transfer request ID, and generates a starting memory address of a tag table based on the Tag ID of the data transfer request. A tag count value is read from the starting memory address of the tag table. If the tag count value reaches a threshold, an absence of a tag overlap is determined and the Tag ID of the data transfer request is added to the tag table at the starting memory address.

Abstract: Various embodiments of the present invention provide systems and methods for out of order memory management. For example, a method for out of order data processing is disclosed. The method includes providing an out of order codeword memory circuit that includes a number of codeword memory locations in a codeword memory area and the same number of index values in an index area. Each of the index values corresponds to a respective one of the codeword memory locations. The methods further include receiving a data set; storing the data set to one of the codeword memory locations; receiving an indication that the data set stored in the one of the codeword memory locations has completed processing; and grouping an index value corresponding to the one of the codeword memory locations with one or more other index values corresponding to unused codeword memory locations.

Abstract: A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.

Abstract: Described embodiments provide a media controller that synchronizes data cached in a buffer and corresponding data stored in one or more sectors of a storage device. A buffer layer module of the media controller caches data transferred between the buffer and the storage device. One or more contiguous sectors are associated with one or more chunks. The buffer layer module updates a status corresponding to each chunk of the cached data and scans the status corresponding to a first chunk of cached data. If, based on the status, the first chunk of cached data is more recent than the corresponding data stored on the storage device, a media layer module synchronizes the data on the storage device with the cached data. The status corresponding to the group of one or more sectors is updated. The media layer module scans a next chunk of cached data, if present.

Abstract: A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such that the bonding pads provide signal communication only for the circuitry.

Abstract: In one embodiment, a matrix-vector multiplication (MVM) component generates a product vector based on (i) an input matrix and (ii) an input vector. The MVM component has a permuter, memory, and an XOR gate array. The permuter permutates, for each input sub-vector of the input vector, the input sub-vector based on a set of permutation coefficients to generate a set of permuted input sub-vectors. The memory stores a set of intermediate product sub-vectors corresponding to the product vector. The XOR gate array performs, for each input sub-vector, exclusive disjunction on (i) the set of permuted input sub-vectors and (ii) the set of intermediate product sub-vectors to update the set of intermediate product subvectors, such that all of the intermediate product sub-vectors in the set are updated based on a current input sub-vector before updating any of the intermediate product sub-vectors in the set based on a subsequent input sub-vector.

Abstract: A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored.

Abstract: Methods and systems for improved transfer of mirrored information between paired dual-active storage controllers in a storage system using a SCSI transport layer. A first portion (approximately half) of the mirrored information transfers are performed in accordance with a first manner in which the controller to receive the mirrored information issues a read operation on the initiator-target nexus (ITN) of the SCSI transport layer to retrieve the mirrored information. A second portion (approximately half) of the mirrored information transfers are performed according to a second manner in which the controller having the information to be mirrored sends the information to be mirrored to the partner controller using a write operation on the ITN. The read and write operations on the same ITN may thus overlap to improve inter-controller communications. The mirrored information may be cached write data or entire I/O requests to be shipped to a partner controller.

Abstract: Methods and structure for improved configuration management of a storage system. A storage system comprises one or more storage controllers coupled with a plurality of storage components (e.g., storage devices and switching components). The coupling often comprises a switched fabric communication structure. Configuration changes normally propagated throughout the components of the networked storage system are prevented by detecting temporary changes in the configuration that are restored to the original configuration within a predetermined period of time. In a Serial Attached SCSI (SAS) storage system, SAS expanders and initiators of the network may be enhanced in accordance with features and aspects hereof to prevent propagation of BROADCAST(CHANGE) primitives when a temporary configuration change is restored within the timeout period. Configuration changes may include temporary loss of link communications for a link of the expander and/or removal and insertion of a storage device coupled with the expander.

Abstract: Methods and apparatus for improved storage network performance by embedding logical volume control within a switching component of a storage network. An enhanced storage network switching component comprises a logical volume manager that aggregates a plurality of ports/PHYS of the switch (each coupled with a corresponding target storage device) to create and manage a logical volume. The manager exposes only a single port/PHY for access to the logical volume. Other ports/PHYs for the individual target storage devices of the logical volume are disabled so that attached host/initiator components cannot access the individual storage devices of the logical volume. In one exemplary embodiment, the logical volume is a striped logical volume to enable parallel operation of multiple storage devices for processing an I/O request. The speed of communications between the switching component and the host/initiator component may then be better matched with the performance of the logical volume.

Abstract: Methods and systems for removably mounting a Solid State Drive (SSD) to a Printed Circuit Board (PCB) device without use of a tool. An exemplary system comprises a top portion and at least two flexible legs. Each leg comprises a vertical member attached to the top portion, and a tab for insertion into the PCB, the tab restricting the motion of the drive enclosure with respect to the PCB when inserted into the PCB, thereby allowing for removable attachment of the enclosure to the PCB without use of a tool. The drive enclosure itself is adapted to receive the SSD and adapted to align the SSD for physical coupling with a connector for the PCB.

Abstract: Exemplary techniques for turning off the clock signal to flip flops are described, which may reduce power consumption by electronic devices. In an implementation, a clock-gating logic turns off the clock signal to a flip flop when a data input of the flip flop remains untoggled. The reduction in power consumption is envisioned to also reduce heat generation.

Abstract: A storage system is configured to determine a redundancy group configuration for a plurality of storage drives by grouping storage drives with a similar performance group designation together. When a storage drive is inserted, the storage system tests the performance of the storage drive. The storage drive may comprise a serial ATA (advanced technology attachment) (SATA) hard drive and/or a solid state drive. The storage system stores the result in a database. The storage system assigns the storage drive a performance group designation based on the result and groups the storage drive into a redundancy group. The storage system then displays the redundancy group configuration for the plurality of storage drives so that a storage administrator may configure the redundancy groupings of the storage drives of the storage system based on the redundancy group configuration displayed.

Abstract: Disclosed are a system and method to preserve and recover unwritten data present in data cache of a disk subsystem across power outages. In one embodiment, a method of a controller is described. The method includes applying a write-back technique between a host server and a data store, accessing a dirty data in a cache memory during a power outage. The method may apply an algorithm for efficiently offloading the dirty data to a non-volatile storage device during the power outage. In addition the method may apply the algorithm to efficiently transfer the dirty data from the non-volatile storage device to the data store when power is restored.

Abstract: Various embodiments of the present invention provide systems and methods for identifying a reproducible location on a storage medium. As an example, a circuit is discussed that includes a data storage circuit, a pattern comparison circuit, and a threshold comparison circuit. The data storage circuit is operable to store a first set of data samples corresponding to a region of interest. The pattern comparison circuit is operable to compare a subset of the first set of data samples with a subset of a second set of data samples corresponding to the region of interest. The pattern comparison circuit is operable to yield a match value corresponding to a degree of similarity between the first set of data samples with the subset of a second set of data samples. The threshold comparison circuit is operable to indicate an anchor point based at least in part on the magnitude of the match value relative to a threshold value.

Abstract: Various approaches for determining storage medium health. For example, a storage device is disclosed that includes a storage medium and a data processing circuit. The data processing circuit receives a data set derived from the storage medium. The data processing circuit includes a data detector circuit, a data decoder circuit, and a health detection circuit. The data detector circuit receives the data set and provides a detected output. The data decoder circuit receives a derivative of the detected output and provides a decoded output. The health detection circuit receives an indication of a number of times that the data set is processed through the combination of the data detector circuit and the data decoder circuit, and generates an indirect health status of the storage medium using the number of times that the data set is processed through the combination of the data detector circuit and the data decoder circuit.

Abstract: A method of resource allocation failure recovery is disclosed. The method generally includes steps (A) to (E). Step (A) may generate a plurality of resource requests from a plurality of driver modules to a manager module executed by a processor. Step (B) may generate a plurality of first calls from the manager module to a plurality of allocation modules in response to the resource requests. Step (C) may allocate a plurality of resources to the driver modules using the allocation modules in response to the first calls. Step (D) may allocate a portion of a memory pool to a particular recovery packet using the manager module in response to the allocation modules signaling a failed allocation of a particular one of the resources. Step (E) may recover from the failed allocation using the particular recovery packet.

Abstract: A parity unit circuit for use in a parallel, pipelined, low density parity check (LDPC) decoder that implements an iterative, min-sum, message passing LDPC algorithm. The parity unit provides a memory logic block for storing information relating to a current and next iteration of the LDPC computations and includes a “compute 1” logic block for computing a parity message (with sign) for application to related bit nodes and a “compute2” logic block for updating the data stored in the memory logic block for a next iteration of the LDPC decoder.

Abstract: Various embodiments of the present invention provide systems and methods for phase offset based spectral aliasing compensation. For example, a circuit for spectral aliasing reduction is disclosed that includes a phase shift circuit operable to phase shift an analog input signal and to provide a phase shifted analog signal; a first analog to digital converter circuit operable to provide a first series of digital samples corresponding to the analog input signal at a sampling frequency; a second analog to digital converter circuit operable to provide a second series of digital samples corresponding to the phase shifted analog signal at the sampling frequency; and an averaging circuit operable to average the first series of digital samples with the second series of digital samples to yield an average output.