Abstract: Various embodiments of the present invention provide systems and methods for servo data based harmonics calculation. For example, a method for calculating harmonics is disclosed that includes: providing a data processing circuit; receiving a first data set derived from a data source during a servo data processing period; performing a first harmonics calculation using the first data set to yield a first harmonics ratio; receiving a second data set derived from a source other than the previously mentioned data source during a user data processing period; performing a second harmonics calculation using the second data set to yield a second harmonics ratio; and calculating a ratio of the first harmonics ratio to the second harmonics ratio.

Abstract: In described embodiments, filter parameters for a filter applied to a signal in, for example, a Serializer/De-serializer (SerDes) receiver and/or transmitter are generated based on real-time monitoring of a data eye. The real-time eye monitor monitors data eye characteristics of the signal present in a data path, the data path applying the filter to the signal. The eye monitor generates eye statistics from the monitored data eye characteristics and an adaptive controller generates a set of parameters for the filter of the data path for statistical calibration of the data eye, wherein the eye monitor continuously monitors the data eye and the adaptive controller continuously generates the set of parameters based on the eye statistics.

Abstract: Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in a volatile memory. At a startup condition of the media controller, a buffer layer module of the media controller allocates space in the volatile memory for one or more logical-to-physical address mapping data structures. A media layer module of the media controller determines a block type of each block of the storage device and places each block of the storage device into corresponding groups based on the determined block type of each block. The one or more blocks of each group are processed, and one or more address mapping data structures for the storage device are constructed in the allocated space in the volatile memory.

Abstract: An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.

Abstract: A method of determining signal routing in an integrated circuit includes providing first coordinates of an input/output cell and second coordinates of an input/output pad to a parametric routing module. The parametric routing module receives at least one wire path parameter. The parametric routing module uses the at least one connection path parameter to determine a physical dimension of a wire path between the first coordinates and the second coordinates.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: A method for capturing data comprising the steps of (A) handling a call for a first operating system at a storage library, (B) routing the call from the storage library to a controller firmware, (C) sending a response to the call from the controller firmware to the storage library, and (D) storing the response in a data store box for later use by the storage library.

Abstract: Described embodiments provide a media controller for processing one or more data transfer requests received from at least one host device. The media controller includes a buffer to receive data of a data transfer request from a communication link and a command parser to generate one or more contexts corresponding to the data transfer request. The one or more contexts are stored in the buffer. At least one queue of the media controller includes a regular context queue for queuing regular-priority contexts, and a high-priority context queue for queuing high-priority contexts. A context manager coordinates processing of regular-priority contexts and high-priority contexts of the at least one queue based on context boundaries, wherein, when a context is processed at a context boundary, data corresponding to the processed context is data is transferred between the communication link and at least one of the buffer and the at least one storage media.

Abstract: A method and system for tracking a sequence of bad blocks in a RAID system by storing the logical block address of the first bad block and the number of bad blocks in the sequence is disclosed. The method and system may also track multiple sequences of bad blocks by storing a memory pointer to the next sequence in each previous sequence in an expandable linked list configuration.

Abstract: A double-step CORDIC algorithm is implemented for conventional signed arithmetic using multiple iteration stages in which at least one stage implements decision postponing, in which the decision for each stage is delayed until the next stage. In one implementation, the decision for the previous stage is implemented in parallel with the execution of CORDIC equation functions for the current stage. Implementing the double-step CORDIC with decision postponing algorithm can increase the speed of the CORDIC function compared to prior-art CORDIC implementations.

Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

Abstract: One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.

Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, a host controller interface (HCI) device includes an isochronous receive first in first out (IRFIFO) buffer. The IRFIFO buffer includes a storage for storing an isochronous data packet received from a guest device. Further, the IRFIFO buffer includes a write pointer for pointing to a write address of the storage for a write operation. Furthermore, the IRFIFO buffer includes a read pointer for pointing to a read address of the storage for a read operation. In addition, the IRFIFO includes a control logic for incrementing the read pointer by a value of a skip parameter of a skip register if the isochronous data packet is not valid for the read operation.

Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, an isochronous data packet placed in an isochronous receive first in first out (IRFIFO) buffer coupled to an isochronous receive direct memory access (IRDMA) is detected. Further, a header of the isochronous data packet is read. Furthermore, a validity of the isochronous data packet is determined. Also, a read operation of remaining data of the isochronous data packet is skipped if the isochronous data packet is determined as invalid.

Abstract: Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (Lch) are adjusted based on the number b of unsatisfied check nodes in the decoded codeword produced by global iteration i?1. The improved turbo-equalization methods can be used as the sole turbo-equalization method for a given global decoding session, or interleaved with other turbo-equalization methods.

Abstract: A method and disk drive for calibrating a phase of a clock in the disk drive. The phase of the clock in the disk drive is changed such that a rate of change for the phase is substantially constant. A pattern of data is written to a magnetic material in the disk drive after the rate of change for the phase becomes substantially constant and while changing the phase of the clock. A selected phase of the clock at which the pattern of data that is written on the magnetic material has a desired quality is identified using the rate of change for the phase, a first point in time at which a timing mark on the magnetic material is read, a second point in time at which the timing mark is read, and a third point in time at which the pattern of data has the desired quality.

Abstract: Various embodiments of the present invention provide for extended life operation of multi-bit memory cells. As an example, some embodiments of the present invention provide electronic systems that include a plurality of multi-bit memory cells, an encoding circuit and a decoding circuit. Each of the plurality of multi-bit memory cells is operable to hold at least two bits. The encoding circuit is operable to receive a data input including at least two data bits, and to encode the two data bits as an encoded output to the plurality of multi-bit memory cells. The encoded output may be selected to be either a single two bit output representing the two bits, or a series of two two bit outputs representing the two bits. The decoding circuit is operable to reverse the encoding applied by the encoding circuit.

Abstract: A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

Abstract: Described embodiments provide encryption/decryption of data transferred between a media controller and a storage device. The media controller provides encryption/decryption based on a root key (RK). Storage in a one-time programmable (OTP) memory is provided as a plurality of un-burned slots. The OTP memory is initially provided without the RK, which is generated with a random number generator. A control module performs the steps of i) burning the RK to an initial slot of the OTP memory, and ii) validating the burned RK (bRK) stored at the initial slot based on a comparison of the RK and the burned RK. If the control module validates the burned RK, the burned RK is employed by the media controller. Otherwise, one or more subsequent slots of the OTP memory are burned with the RK until the control module validates the corresponding burned RK.

Abstract: Methods and apparatus are provided for CDR and equalization update qualification. A block of received data comprising a plurality of multiple tone patterns is processed. Equalization adaptation and/or updates to a timing recovery process can be selectively disabled if one or more of the multiple tone patterns exceed a corresponding predefined threshold.