Abstract: A DCT-based technique with rhombus scanning for image compression. A flipped-kernel discrete cosine transform is applied to an eight by eight pixel sub-block of the sixteen by sixteen pixel block. A visually insignificant information is removed from the eight by eight pixel sub-block. A quantization method is used to remove the visually insignificant information. A quantized discrete cosine transform coefficient is scanned of the sixteen by sixteen pixel block. The quantized discrete cosine transform coefficient is scanned according to a rhomboid pattern. A portion of a digital image may be divided into a sixteen by sixteen pixel block.

Abstract: An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.

Abstract: An apparatus comprising an estimation circuit, a rate control circuit, a queue circuit, and an encoder circuit. The estimation circuit may be configured to generate a size value in response to an input signal comprising (i) a plurality of frames and (ii) a plurality of embedded subtitle elements. The rate control circuit may be configured to (i) generate a control signal, (ii) pass through the plurality of frames, (iii) present a first one or more of subtitle elements for current processing in response to the size value, and (iv) present a second one or more of subtitle elements for subsequent processing. The queue circuit may be configured to (i) receive the second one or more subtitle elements, (ii) present the second one or more of subtitle elements for current processing when the control signal is in a first state and (iii) hold a second one or more subtitle elements for subsequent processing when the control signal is in a second state.

Abstract: Various approaches related to systems and methods for reusing decoding parity.

Abstract: In one embodiment, a reconfigurable minimum operator has two five-bit non-reconfigurable minimum operators and is selectively configurable to operate in a five- or ten-bit mode. In five-bit mode, the first non-reconfigurable minimum operator determines whether a first five-bit message is less than a second five-bit message, and the second non-reconfigurable minimum operator determines whether a third five-bit message is less than a fourth five-bit message. In ten-bit mode, the first non-reconfigurable minimum operator determines whether a first half of a first ten-bit message is less than a first half of a second ten-bit message, and the second non-reconfigurable minimum operator determines whether a second half of the first ten-bit message is less than a second half of the second ten-bit message. The reconfigurable minimum operator determines whether the first ten-bit message is less than the second ten-bit message based on the comparisons of the first and second non-reconfigurable minimum operators.

Abstract: In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another.

Abstract: A mobile communication device having a plurality of mobile devices coupled to one another. The mobile communication device includes a first mobile device that has a screen display portion and a user input portion. The mobile communication device also includes at least one second mobile device detachably coupled to the first mobile device. The first mobile device is configured to function as a first standalone mobile communication device, and the second mobile device is configured to function as a second standalone mobile communication device when detached from the first mobile device. The second mobile device is detachably coupled to the first mobile device in such a way that the first mobile device continues to include the display screen portion and the user input portion when the second mobile device is detached from the first mobile device.

Abstract: A computer-executed method for designing dummy metal object locations in an integrated circuit design. The method comprises the steps of: a) receiving an integrated circuit design as input; b) finding areas of the integrated circuit design that do not meet a minimum metal density requirement; c) finding areas of the integrated circuit design having a critical timing path; d) blocking empty routing tracks that are adjacent to critical nets of the critical timing paths located in step (c), for prospective dummy metal object placement for the areas commonly located in both of steps (b) and (c); and e) placing a minimum number of dummy metal objects in empty tracks such that the minimum metal density requirement is met for the areas that were found in step (b), but were not blocked in step (d).

Abstract: The disclosure provides a speech encoder, decoder, speech processor and methods of encoding and decoding speech. In one embodiment, the speech encoder includes: (1) a speech frame generator configured to form a speech frame from an input speech signal, the speech frame having a length of multiple samples, (2) a speech frame processor configured to determine if the speech frame is a subsequent voiced frame of a group of consecutive voiced frames and, based thereon, perform speech analysis of the subsequent voiced frame; and (3) a speech frame coder configured to perform, if the speech frame is a subsequent voiced frame, differential coding of speech parameters of the subsequent voiced frame with respect to previous speech parameters of the previous voiced frame of the consecutive voiced frames.

Abstract: A lead-free solder joint is formed between a tin-silver-copper solder alloy (SAC), SACX, or other commonly used Pb-free solder alloys, and a metallization layer of a substrate. Interaction of the SAC with the metallization layer forms an intermetallic compound (IMC) that binds the solder mass to the metallization layer. The IMC region is substantially free of any phosphorous-containing layers or regions.

Abstract: A surgical pledget assembly includes a pledget body having first and second apertures extending through the body, one or more snares passing through the apertures in the pledget body and including first and second suture engaging loops disposed on a distal side of the pledget, an optional third folding loop disposed on a proximal side of the pledget, and a handle secured to the ends of the snare or snares proximal to the pledget.

Abstract: In one embodiment of the invention, decompressed video signals are upscaled and then filtered using a combined mosquito noise reduction (MNR) and aliasing coring filter that reduces both mosquito noise in the decompressed video signals as well as aliasing noise resulting from the upscaling process. In one implementation, the combined coring filter includes a dual-band filter having two passbands interleaved with two stopbands. The strength of the coring filter may be dynamically controlled based on compression information (e.g., quantizer scales indicative of video quality) associated with the compressed video bitstream from which the decompressed video is recovered.

Abstract: In one embodiment, a reconfigurable two's-complement-to-sign-magnitude (2TSM) converter has two five-bit non-reconfigurable 2TSM converters and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second five-bit messages, respectively, from two's-complement-to-sign-magnitude format. In the ten-bit mode, the first and second non-reconfigurable 2TSM converters concurrently convert first and second halves of a ten-bit message, respectively, from two's-complement-to-sign-magnitude format. The reconfigurable 2TSM converter then generates a ten-bit sign-magnitude message based on the conversions of the two non-reconfigurable 2TSM and a carry-over bit. In another embodiment, a reconfigurable sign-magnitude-to-two's-complement (SMT2) converter comprises the reconfigurable 2TSM described above.

Abstract: A MOS-type semiconductor clamping circuit is disclosed. The clamping circuit comprises a pmos device coupled to a nmos device in series to form the clamping circuit to selectively clamp a signal to a reference voltage, the signal configured to swing between a first voltage and a second voltage about the reference voltage. When the signal is swung between the first voltage and the second voltage, the pmos device and the nmos device are subjected to a voltage swing less than the voltage swing between the first voltage and the second voltage.

Abstract: Methods and structure for diagnosing errors in the initialization of DDR memory “on board” a storage controller or a storage expander are presented herein. The features and aspects discussed herein allow for the debugging of the DDR memory initialization. A memory diagnostic system is operable on a storage controller and includes an initialization module in communication with a firmware module of the storage controller. The memory diagnostic system is adapted to initialize a Double Date Rate (DDR) memory of the storage controller. The memory diagnostic system also includes an application programming interface adapted to retrieve initialization information from the initialization module and transfer the initialization information to a debug system via a direct communication link between the application programming interface and the debug system to diagnose the initialization of the DDR memory and to debug the initialization module based on the initialization information.

Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

Abstract: A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

Abstract: An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.

Abstract: A method of controlling spinning of data disk drives, a data storage system including multiple data disk drives and a power zone aware device are disclosed herein. In one embodiment, the power zone aware device includes: (1) a policy module configured to define at least one power zone in the data storage system and assign a power zone policy thereto and (2) a management module coupled configured to direct operation of data disk drives in the power zone based on the power zone policy.

Abstract: A SAS expander for use in a SAS topology includes a receiving portion and a controller. The receiving portion is configured to receive a remote RAID instruction from a root host bus adapter. The controller is configured to execute the instruction to manage a RAID volume in accordance with a RAID management task specified by the instruction.