Abstract: An apparatus comprises digitally controlled oscillator circuitry, feedback circuitry operatively coupled to the digitally controlled oscillator circuitry, and comparison circuitry operatively coupled to the digitally controlled oscillator circuitry and the feedback circuitry. The feedback circuitry, in response to a clock signal generated by the digitally controlled oscillator circuitry, generates a first digital value representing a detected phase of the clock signal for a given clock signal cycle. The comparison circuitry, in response to the first digital value and to a second digital value representing a reference phase, generates a phase error value. The phase error value is useable to generate a first digital control word provided to the digitally controlled oscillator circuitry for controlling a frequency associated with the clock signal.

Abstract: An apparatus comprising an interface, a first port, and a second port. The interface may be configured to connect to a host computer. The first port may be configured to connect to a first set of storage devices using a first protocol. The second port may be configured to connect to a second set of storage devices using a second protocol. The apparatus may provide support for the first protocol and the second protocol to allow communication using both the first protocol and the second protocol through the interface.

Abstract: Methods and apparatus are provided for automatic gain control in a receiver using samples taken at a desired sampling phase and target voltage level. The gain of a received signal is adjusted by obtaining a plurality of samples of the received signal substantially at a desired sampling phase (such as a center of a given unit interval), wherein at least one of the samples is taken substantially at a target voltage level; comparing the plurality of samples to determine whether the received signal has an amplitude that is substantially equal to the target voltage level; and adjusting a receiver gain based on whether the received signal amplitude is substantially equal to the target voltage level. The comparison can comprise the evaluation of a logic function, such as an exclusive OR function. The comparison can be performed over a plurality of samples to obtain an average gain update decision.

Abstract: An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core.

Abstract: A system and method for designing circuits, such as integrated circuits, that allow a designer to employ mixed cell libraries. In one embodiment, the system includes: (1) a cell placement EDA tool configured to transform a logical circuit representation into a physical circuit representation by placing cells from mixed cell libraries into clusters corresponding to the mixed cell libraries and (2) an interconnect routing EDA tool associated with the cell placement EDA tool and configured to route interconnects in buffer zones separating the clusters.

Abstract: Provided is a voltage discharging device. The voltage discharging device includes a battery, an inverter converting a DC power supplied from the battery into an AC power to output the converted AC power, a motor driven by the AC power outputted through the inverter, a main relay disposed between the battery and the inverter to switch the DC power supplied from the battery into the inverter, and a control unit detecting a key-off signal of the vehicle to discharge a DC link voltage of the inverter when the key-off signal is detected. The control unit discharges the DC link voltage by applying one of first and second forced discharging logics different from each other according to a driving state of the vehicle at a time point at which the key-off signal is detected.

Abstract: A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level.

Abstract: A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is created. In the degraded netlist, the first transistor is degraded by a device degradation for the first transistor. The second transistor is degraded by a device degradation for the second transistor. The circuit is re-simulated with the first degraded transistor and the second degraded transistor in place of the first MOS transistor.

Abstract: An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core.

Abstract: A lighting device having a support module supporting LEDs and having an outer perimeter defining a curved portion, and a housing with an inner surface having a curved portion configured to receive the curved portion of the support module to enable the disk to be aimed, while the curved portions of the disk and housing remain in contact. Optional adjustment means facilitate aiming of the support module without the need to open the sealed LED module.

Abstract: A method of adjusting an expected lifetime equation that includes measuring, for a MOS integrated circuit fabrication process, a first dependence of a saturation current (Idsat) degradation versus gate voltage (Vgs). This first dependence is indicative of Idsat degradation at least partially caused by hot carrier injection (HCI). A second dependence of the saturation current (Idsat) degradation versus gate voltage (Vgs) is also measured. This second dependence is indicative of Idsat degradation caused by bias temperature instability (BTI). An artificial HCI lifetime equation is determined. This artificial HCI lifetime equation is based on the second dependence subtracted from the first dependence. A circuit having at least one MOS transistor that includes a first MOS transistor is simulated. Based on the results of the simulation, and the artificial HCI lifetime equation, an Idsat degradation for the first MOS transistor is calculated.

Abstract: A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated.

Abstract: A method for checking for reliability problems includes simulating a circuit having at least one MOS transistor that includes a first MOS transistor. Based on the results of this simulation of the circuit, a gate-to-bulk voltage (Vgb) for the first MOS transistor is calculated. A voltage limit based on the length of the channel of the first MOS transistor is selected. If Vgb is greater than the voltage limit, a warning message is generated.

Abstract: A method for checking for reliability problems includes measuring, for a MOS integrated circuit fabrication process, a dependence of a saturation current (Idsat) degradation versus gate voltage (Vgs). The saturation current (Idsat) degradation versus drain voltage (Vds) is also measured for the MOS integrated circuit process. The measured data points of an amount of time until a threshold degradation occurs versus Vgs divided by Vds is fitted to a curve in order to determine a first expected lifetime equation that is based on Vgs. A circuit having at least one MOS transistor that includes a first MOS transistor is simulated. Based on the results of this simulation, and the first expected lifetime equation, a first expected lifetime for the first MOS transistor is calculated. If the first expected lifetime is less than a lifetime limit, a warning message is generated.

Abstract: A light-emitting diode (LED) apparatus comprises a substrate, a first layer formed over at least a portion of the substrate, an active layer formed over at least a portion of the first layer, a second layer formed over at least a portion of the active layer, and at least one waveguide formed below the substrate. A first portion of light from the LED is directed in a first direction and a second portion of light from the LED is directed in a second direction via the waveguide, the second direction being different than the first direction. The apparatus may further comprise a shutter formed at least one of above and below the waveguide, the shutter being adjustable to control an amount of light entering or exiting the waveguide.

Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.

Abstract: A method of determining a saturation current degradation that includes measuring, for a MOS integrated circuit fabrication process, a first dependence of a saturation current (Idsat) degradation with gate voltage (Vgs) at a level that causes Idsat degradation by bias temperature instability (BTI). A second dependence of the saturation current (Idsat) recovery versus gate voltage (Vgs) is also measured for the MOS integrated circuit fabrication process. A recovery voltage threshold value is determined. The recovery voltage threshold value is indicative of Vgs voltages below which BTI recovery occurs. A circuit having at least one MOS transistor that includes a first MOS transistor is simulated. Based on the results of the simulation, a BTI recovery factor is calculated based on an amount of time the Vgs of the first MOS transistor is below the recovery voltage threshold value.

Abstract: A system is described for recovering data from a number of sectors, such as the sectors of a hard disk drive (HDD) disk platter, and so forth. The system receives data from the sectors via a read channel and uses a layered data decoder to recover data from the sectors. A memory is coupled with the processor and configured to retain data received from one or more of the sectors, e.g., in retained sector reprocessing (RSR) embodiments. The system is configured to update messages in different circulant layers of the data decoder's parity-check matrix. The system uses one message update order in a processing iteration, and different message update orders in subsequent reprocessing iterations. In some embodiments, layer reordering is used for RSR. In some embodiments, circulant reordering is used for RSR.

Abstract: A method for checking for reliability problems that includes simulating a circuit having at least one MOS transistor. The circuit includes at least a first MOS transistor. Based on the results of the simulation of the circuit, a bulk-to-source voltage (Vbs) is calculated for the first MOS transistor. Based on the calculated Vbs for the first MOS transistor, a threshold voltage (Vth) for the first MOS transistor is calculated. Based on the Vth, an effective Vgs for the first MOS transistor is calculated. And, based on the effective Vgs, a reliability indicator associated with the first MOS transistor is calculated.

Abstract: Systems and methods for computing sign disagreement between Le and La signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector.