Abstract: A filter assembly is provided. The filter assembly includes a printed circuit board (PCB) including a plurality of electronic components, a base disposed under the PCB, and an inductor coupled to the base, the inductor including a core and a coil to which current is applied, wherein the PCB has a through-hole through which at least one portion of the coil pass.

Abstract: Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal.

Abstract: The invention provides an elastic or flexible SSD cache utilizing a hybrid RAID protocol combining RAID-0 protocol for read data and RAID-5 single parity protocol for write data in the same cache array. Read data may be stored in window sized allocations using RAID-0 protocol to avoid allocating an entire RAID stripe for read cache data. In the same SSD volume, dirty write data is stored in row allocations using RAID-5 protocol to provide single parity for the dirty write data. Read data is typically stored a window from the physical device having the largest number of available windows. Write data is stored in a row including the next available window in each arm, which decouples the window structure of the rows from the stripe configuration of the physical memory devices.

Abstract: Coding circuitry comprises at least an encoder configured to encode an instruction address for transmission to a decoder. The encoder is operative to identify the instruction address as belonging to a particular one of a plurality of groups of instruction addresses associated with respective distinct program constructs, and to encode the instruction address based on the identified group. The decoder is operative to identify the encoded instruction address as belonging to the particular one of a plurality of groups of instruction addresses associated with respective distinct program constructs, and to decode the encoded instruction address based on the identified group. The coding circuitry may be implemented as part of an integrated circuit or other processing device that includes associated processor and memory elements. In such an arrangement, the processor may generate the instruction address for delivery over a bus to the memory.

Abstract: An apparatus for estimating a parameter of an induction motor is provided. The estimating apparatus receives an output from a current controller and d and q-axis currents in a synchronous reference frame applied to an induction motor, calculates an error of rotor resistance, and obtains a difference between the rotor resistance and nominal rotor resistance.

Abstract: An inverter device may include a converter unit configured to receive single phase AC power to output DC power; a capacitor unit configured to absorb the DC power; an inverter unit configured to synthesize the absorbed DC power to output the drive power of a load; and a converter controller configured to control the converter unit based on the AC power and the output DC power of the converter unit, wherein the converter controller includes a converter gate signal generator configured to control a plurality of gates contained in the converter unit; and an input line harmonic voltage generator configured to output converter additional power having a predetermined multiple of the frequency of the fundamental frequency component of the AC power with the same size as that of the fundamental frequency component of the AC power to an adder connected to the input side of the converter gate signal generator.

Abstract: An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.

Abstract: A memory content access interface may include, but is not limited to: a read-path memory partition; a write-path memory partition; and a memory access controller configured to regulate access to at least one of the read-path memory partition and the write-path memory partition by an external controller.

Abstract: A sense amplifier enable signal delay circuit for the programmable control of the delay of the generation of a sense amplifier enable signal is described. Further, stacked transistors and a pulse-width control block, which are programmed by external test pins to control the delay of the generation of a sense amplifier enable signal are described. Methods associated with the use of the sense amplifier enable signal delay circuit and for the sense amplifier enable signal generation delay are also described.

Abstract: Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component code word; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the first convergence of at least one component codeword; determining a second convergence value associated with the at least one component codeword according to the extrinsic data associated with the at least one component codeword.

Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.

Abstract: Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The SAS expander also includes a Content Addressable Memory (CAM) including entries that each associate a SAS address with an entry in the routing memory. Further, the SAS expander includes a controller that receives a request for a SAS address, uses the CAM to determine a corresponding routing memory entry for the requested SAS address, and selects the port indicated by the corresponding routing memory entry.

Abstract: An electric vehicle charger includes a case including a lower case having an opened top surface and in which a connector insertion groove is defined in a side surface thereof and an upper case having an opened bottom surface and covering the opened top surface of the lower case, a circuit board seated on the lower case and on which at least one electrical component of a short-circuit detection part detecting short-circuit of an electric vehicle, a detection part detecting overvoltage and overcurrent during charging of the electric vehicle, a communication module communicating with a charging control part of the electric vehicle, and a display part displaying a charged state of the electric vehicle is mounted, a cable inserted into the lower case, the cable being electrically connected to the circuit board, and a cable connector inserted into the connector insertion groove to guide the insertion of the cable.

Abstract: A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.

Abstract: Provided is a trip button mechanism of an external handle for a circuit breaker. The trip button mechanism includes a button support, an externally operable trip button, and an elastic member. The button support is disposed at an outer casing of the externally operable handle and exposed through a penetration hole of the outer casing. The externally operable trip button includes a handle exposed through the penetration hole and a pusher in one piece with the handle. The pusher is movable along the button support for pushing a circuit breaker trip button. The elastic member applies a force to the externally operable trip button in a direction opposite to a direction in which the externally operable trip button pushes the circuit breaker trip button. Therefore, the trip button mechanism can be easily assembled to increase productivity and decrease manufacturing costs, and the trip button mechanism can be reliably operated.

Abstract: Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a noise predictive filter circuit, a scaling factor adaptation circuit, and a scaling factor application circuit. The noise predictive filter circuit is operable to perform a noise predictive filtering process on a data input based on a filter tap to yield a noise filtered output. The scaling factor adaptation circuit is operable to calculate a scaling factor based at least in part on a derivative of the noise filtered output. The scaling factor application circuit is operable to apply the scaling factor to scale the noise filtered output.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a codeword detector circuit operable to apply a codeword based data detection algorithm to a data input corresponding to an encoded servo data region to yield a detected output, and a servo address mark processing circuit operable to identify a pre-defined pattern in the detected output.

Abstract: A method includes associating a spatially separate audio sensor and/or a vibration sensor with an audio processing system having one or more audio sensor(s) associated therewith. The spatially separate audio sensor is on a remote location distinct from that of the one or more audio sensor(s). The method also includes capturing information uniquely associated with an external environment of the audio processing system through the spatially separate audio sensor and/or the vibration sensor and the one or more audio sensor(s), and adapting an audio output of the audio processing system based on the captured information uniquely associated with the external environment thereof.

Abstract: Provided are a device and method of stopping an induction motor. The includes: a frequency commanding unit for generating an operating frequency corresponding to a rotational speed command of the induction motor; a q-axis and d-axis V/F converter for outputting a first q-axis voltage (Vq1) proportional to the generated operating frequency and a first d-axis voltage (Vd1) proportional to a 0 frequency; a q-axis PI current controller for outputting a second q-axis voltage (Vq2) for stopping the induction motor when the operating frequency reaches a stopping frequency; a d-axis PI current controller for outputting a second d-axis voltage (Vd2) for stopping the induction motor when the operating frequency reaches the stopping frequency; and a selection unit for selecting and outputting the first q-axis and d-axis voltages (Vq1 and Vd1) or the second q-axis and d-axis voltages (Vq2 and Vd2) according to the operating frequency generated by the frequency commanding unit.