Abstract: A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow portion and the early design flow portion and (3) a modeler configured to develop a model for a top level implementation of the IC design based on the timing budget and block implementations generated during the late design flow portion.

Abstract: Described embodiments provide a wideband code division multiple access (W-CDMA) system that employs a rate matching rule having a modified puncturing algorithm. The modified puncturing algorithm defines the input variables of the rate matching rule in a manner that provides for identification of relations between non-punctured data bit position addresses in the output data stream through an iterative process, from which absolute bit position addresses of non-punctured output bits might then be generated. A counter, in accordance with instruction generated by a processor or state machine, for example, might implement the modified puncturing algorithm on an input string of bits to provide an output string of bits based on the absolute bit position addresses of non-punctured output bits, thereby providing for rate matching in the communications channel.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding system.

Abstract: In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations of unsatisfied check nodes of the last local decoder iteration and selecting the equalized samples that correspond to bit nodes of the LDPC-encoded codeword that are connected to the unsatisfied check nodes. Adjustment of the equalized samples may be performed using any combination of scaling, offsetting, and saturation. Channel detection is then performed using the adjusted equalized samples to generate an updated set of channel soft-output values, which are subsequently decoded by the decoder.

Abstract: A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams, a map stream, and a checkpoint stream. Host data is written to the data streams, map entries are written to the map stream, and checkpoints of map entries and other data structures are written to the checkpoint stream. Time markers embedded in the streams enable determination, during recovery, that selected portions of the streams are inconsistent with each other and are to be discarded.

Abstract: A parallel meter-reading method between a concentrator and electricity meters includes determining a phase of electric power supplied from a concentrator to the electricity meters, generating a reference signal synchronized with electric power determined for each phase, generating a request signal synchronized with the 3 phases electric power determined and transmitting the generated request signal to an electricity meter modem, receiving the request signal, determining a phase of electric power supplied to the electricity meter according to the request signal, generating a response signal synchronized with the determined phase and transmitting the generated response signal to the concentrator modem, and receiving the response signal of the electricity meter modem with respect to the request signal, and determining whether or not the response signal is synchronized with the reference signal to determine the phase of electric power supplied to the electricity meter.

Abstract: An apparatus comprises a direct digital synthesizer, a mixer having first and second input ports and an output port, and a numerically-controlled oscillator. The direct digital synthesizer has a first output coupled to the first input port of the mixer and a second output coupled to a control input of the numerically-controlled oscillator, and the numerically-controlled oscillator has an output coupled to the second input port of the mixer. The mixer provides a quadrature modulated signal at its output port, and the first and second outputs of the direct digital synthesizer control respective portions of the quadrature modulated signal. For example, the first and second outputs of the direct digital synthesizer may control respective amplitude and phase portions of the quadrature modulated signal.

Abstract: An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller determines that an error reading a page of NVM was caused by cell damage and/or cell leakage. The controller reprograms and immediately reads back the page, detecting that the error was caused by cell damage if an error is detected during the immediate read. In a second aspect, the cell damage is tracked by updating cell damage counters for pages and/or blocks of NVM. In a third aspect, wear leveling is performed based at least in part upon measured cell damage for pages and/or blocks of NVM.

Abstract: An apparatus comprises a substrate, a first buried layer formed over the substrate, the first buried layer comprising one or more raised mesa structures, a second buried layer formed over the first buried layer, an active layer formed over the second buried layer, and a capping layer formed over the active layer. The apparatus may further comprise a third buried layer formed over the active layer, the third buried layer comprising one or more raised mesa structures, and a fourth buried layer formed over the third buried layer. The one or more raised mesa structures of the first buried layer may be offset from the one or more raised mesa structures of the third buried layer.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.

Abstract: The embodiment relates to a transformer. A transformer according to an aspect includes: a first coil assembly including a first core, a first bobbin coupled to the first core, and a first coil provided on the first bobbin; and a second coil assembly coupled to the first coil assembly, and including a second core, a second bobbin coupled to the second core, and a second coil provided on the second bobbin.

Abstract: Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for format efficient data processing.

Abstract: A device for aggregating flash modules includes a switch to connect to a plurality of servers and a midplane to connect to a plurality of flash modules. The switch and midplane are connected such that the switch can route data traffic to any of the plurality of flash modules, and the plurality of servers can connect to the plurality of flash modules transparently, as if a flash module was directly installed into a server.

Abstract: In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding subword encoders/decoders in the different subword-processing paths perform subword encoding/decoding with different encoder/decoder matrices.

Abstract: Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of symbols and (ii) a plurality of decision values both in response to detecting an encoded codeword. The second circuit may be configured to (i) generate a plurality of probabilities to flip one or more of the symbols based on the decision values, (ii) generate a modified probability by merging two or more of the probabilities of an unreliable position in the symbols and (iii) generate a decoded codeword by decoding the symbols using a list decode technique in response to the modified probability.

Abstract: Methods and apparatus are provided for interfacing between a flash memory controller and a flash memory array. The interface comprises a communication channel between the flash memory controller and the flash memory array, wherein the communication channel carries data for a target cell in the flash memory array on a first edge of a clock signal and wherein the communication channel carries additional information for the target cell on a second edge of the clock signal. For an exemplary write access, the additional information comprises, for example, information about one or more aggressor cells associated with the target cell. For an exemplary read access, the additional information comprises, for example, soft information for the data for the target cell transmitted on the first edge.

Abstract: An apparatus comprising a controller circuit and an array. The controller circuit may be configured to read/write data in response to one or more input/output requests. The array may be configured to present/receive data to/from the controller circuit in response to the input/output requests. The data may be only transmitted to/from the array after a successful authentication between (i) a first code embedded within each of the input/output requests and (ii) a second code stored on a non-volatile memory within the controller circuit.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises transition control circuitry configured to detect transitions between binary logic levels in a scan test signal, and responsive to a number of detected transitions reaching a threshold, to limit further transitions associated with a remaining portion of the scan test signal. In an illustrative embodiment, the transition control circuitry limits further transitions associated with the remaining portion of the scan test signal by replacing at least part of the remaining portion of the scan test signal with a limited transition signal. The limited transition signal may be maintained at a constant binary logic level such that it has no transitions. By limiting the number of transitions associated with the scan test signal, the transition control circuitry serves to reduce integrated circuit power consumption during scan testing.