Abstract: Embodiments of the invention provide a method associated with a RAID configuration, wherein RAID storage volumes are created by RAID controllers from a shared pool of disk drives. A specified RAID volume is mapped to a virtual target port, and is accessed by each of one or more servers via the virtual target address. One embodiment of the invention is directed to a method associated with multiple RAID controllers, and a pool of disk drives that comprises multiple storage disks. The method comprises operating one or more of the RAID controllers to each configure one or more RAID volumes from selected storage disks. A unique identifier is assigned to each of the RAID volumes, wherein a specified RAID volume is assigned a specified unique identifier, and a particular RAID controller is provided with ownership of the specified RAID volume at a particular time.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.

Abstract: The present inventions are related to apparatuses and methods for detecting and classifying media defects. For example, an apparatus for classifying a media defect is disclosed including a DFT circuit operable to yield real and imaginary components of a signal derived from data read from a storage medium, a calculation circuit operable to calculate an amplitude and a phase of the signal based on the real and imaginary components, and a classifier operable to detect the media defect based on the amplitude and to classify the media defect based on the phase.

Abstract: Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof.

Abstract: An apparatus and method to allocate memory in a storage system. Firmware running the method uses an iterative approach to find the best optimal memory configuration for a particular storage system given a variety of configuration data parameters stored as persistent data in non-volatile flash memory. The configuration data relates to resources in the environment that the storage system is found in, such as the number of virtual ports, targets and initiators supported by a storage system IOC. The configuration data is alterable, to allow flexibility in updating and changing parameters, and is employed at runtime when the storage system powers on, to enable the most flexible resource allocation.

Abstract: A track-and-hold circuit comprises at least first and second amplifier stages, and switched capacitor circuitry coupled between the first and second amplifier stages. In a track mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to decouple inputs of the second amplifier stage from respective outputs of the first amplifier stage and to couple the inputs of the second amplifier stage to a common mode voltage via respective first and second capacitors. In a hold mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to couple the inputs of the second amplifier stage to the respective outputs of the first amplifier stage via the respective first and second capacitors. Multiple instances of the track-and-hold circuit may be implemented in parallel in a time-interleaved analog-to-digital converter.

Abstract: Provided is a coupling assembly of a power semiconductor device and a printed circuit board (PCB). The coupling assembly of the power semiconductor device and the printed circuit board (PCB) includes a PCB, a power semiconductor device comprising a plurality of legs electrically connected to a circuit pattern disposed on the PCB, a connection member disposed above the power semiconductor device, the connection member being formed of an electrically conductive material, a main fixing unit fixing the power semiconductor device to the PCB, and a housing disposed outside the PCB. Thus, a coupling force between the power semiconductor device and the PCB and electric efficiency may be improved to a heat generation amount. In addition, heat may be more quickly dissipated through the connection member to improve a cooling effect.

Abstract: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.

Abstract: Apparatus and devices for carrying a storage device and adapting it to a slot for a storage device having a different form factor. The system comprises an opening means for elastically deforming a shape of the system from an original shape so that the carrier may receive the storage device. The system also comprises restraining means for constraining the motion of the storage device within the system when the system returns to the original shape. Furthermore, the system comprises a spacing means for aligning the storage device with the slot while the storage device is restrained within the system.

Abstract: A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses codeword/waveform classification to accelerate simulation of the read-channel's error-rate characteristics, with said classification being generated using a first read-channel simulator having a limited functionality. A second read-channel simulator having an extended functionality is then run only for some of the codewords, with the latter having been identified based on said codeword/waveform classification. The acceleration is achieved, at least in part, because the relatively highly time-consuming processing steps implemented in the second read-channel simulator are applied to fewer codewords than otherwise required by conventional simulation methods.

Abstract: A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes.

Abstract: A train control system is disclosed, the system including a biometric information input device configured to receive a driver's biometric information through a sensor and to transmit the driver's biometric information to a cab signal device, wherein the cab signal device compares the biometric information of a driver intending to operate a train with a pre-registered driver's biometric information to verify a relevant driver, and verification of a driver intending to operate a train is realized by biometric information, and unauthorized person's access can be fundamentally avoided because biometric information cannot be copied or leaked due to person's biometric information being intrinsic.

Abstract: Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts.

Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to ?; and computing a fine corrective value using a polynomial approximation.

Abstract: A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

Abstract: A hard disk drive or other storage device comprises a storage medium, a read head configured to read data from the storage medium, and control circuitry coupled to the read head and configured to process data received from the read head. The control circuitry comprises read channel circuitry that includes a low-density parity check decoder or other type of decoder. Power management circuitry associated with the read channel circuitry is configured to detect a power control condition of the read channel circuitry and to control insertion of idle clock cycles in a clock signal supplied to the decoder responsive to the detected power control condition. For example, the read channel circuitry may comprise a clock generator configured to gate the clock signal responsive to a control signal from the power management circuitry.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to generate a degauss signal to be applied to the write head by the write driver. The degauss signal has a waveform comprising a plurality of decay segments including at least one alternating current decay segment and at least one direct current decay segment. An initial decay segment of the plurality of decay segments may comprise an alternating current decay segment or a direct current decay segment, and may be immediately followed by a decay segment of the opposite type.

Abstract: A memory device comprises a memory array and associated control circuitry. The control circuitry comprises a clock generator configured to generate a clock signal for controlling timing of at least one of a read operation and a write operation directed to the memory array. The clock generator comprises a plurality of sets of address change detection circuits. The sets are configured to generate respective output signals as a function of respective subsets of address bits of an address signal identifying an address in the memory array. The clock generator further comprises logic circuitry coupled to the sets of address change detection circuits and configured to receive the respective output signals therefrom and to generate the clock signal as a function of said output signals.

Abstract: A stationary contact arm assembly for a molded case circuit breaker includes a stationary contact arm having a terminal portion and a contact portion provided at both end portions thereof in the length direction, and an inclined extension portion provided between the contact portion and the terminal portion, a flat extension portion forming a space between the flat extension portion and a bottom surface of the contact potion, a bent portion formed from the flat extension portion to the terminal portion; a magnet assembly having a plurality of steel plates at least part of which is installed to be pushed into a space between the flat extension portion and contact portion in the stationary contact arm; and an elastic support plate having an elastic support portion installed on the flat extension portion of the stationary contact arm to support the magnet assembly.

Abstract: A high-frequency supply voltage waveform is sampled from a functioning integrated circuit. This waveform is measured at (or coupled closely to) a power supply node on the integrated circuit. A low-frequency supply current waveform is sampled concurrently with the sampling the high-frequency supply voltage waveform. This waveform is measured at a power supply node external to the integrated circuit. A power supply network providing power to the integrated circuit is modeled with a circuit model. The power supply network is modeled using the high-frequency supply voltage waveform as an input to the circuit model. A simulation output is taken at a simulated power supply node corresponding to the power supply node external to said integrated circuit. Based on a comparison of the simulated low-frequency supply current waveform and the low-frequency supply current waveform, a value of at least one component of the circuit model is adjusted.