Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.

Abstract: A storage system comprising: a SCSI initiator being configured for receiving a data request and providing a SMP request corresponding to the data request, the SCSI initiator being further configured for encapsulating the SMP request into a first SCSI command; a SCSI target being configured for receiving the first SCSI command, the SCSI target being further configured for recognizing encapsulation of the SMP request and obtaining the SMP request from the first SCSI command; and an SMP target being configured for processing the SMP request and providing an SMP response to the SCSI target. The SCSI target being further configured for acknowledging the SCSI initiator upon reception of the SMP response; and the SCSI initiator being further configured for sending a second SCSI command to the SCSI target to retrieve the SMP response.

Abstract: Aspects of the present disclosure relate to cloud computing-based data sharing system and method, the system including a plurality of industrial device management units configured to transmit a recent shared data to a cloud server by periodically communicating with the cloud server, to receive a recent shared data of other industrial device management units received from the cloud server and to synchronize the shared data by updating the recent shared data to its own shared data, and a cloud server configured to compare a received shared data with a pre-stored shared data, in a case a shared data is received form an industrial device management unit among the plurality of industrial device management units through a communication network, to update its shared data as a result of the comparison, and to transmit a notification message including the updated shared data to other industrial device management unit through the communication network.

Abstract: A device includes a disk drive assembly configured to store information using a platter comprising a magnetic material surface and a magnetic head disposed above the magnetic material surface. The magnetic head is configured to move across tracks formed on the platter to write information to the magnetic material surface and read information from the magnetic material surface. The device also includes a controller operatively coupled with the disk drive assembly. The controller is configured to dynamically adjust the height of the magnetic head above the magnetic material surface at each of the tracks by determining a harmonic ratio for a particular track and comparing the harmonic ratio to a reference harmonic ratio for the track. For example, the controller calculates a difference between the harmonic ratio and the reference harmonic ratio.

Abstract: Storage device FirmWare (FW) and manufacturing software techniques include access to FW images and communication of a manufacturing software tool. The manufacturing software tool enables download of the FW images into an I/O device and controlling a manufacturing test of the I/O device that is a storage device providing a storage capability. Execution of the downloaded FW images enables an I/O controller of the I/O device to provide the storage capability via operation with one or more selected types of flash memory devices. The selected types are selected from a plurality of flash memory types that the I/O controller is capable of operating with by executing appropriate ones of the FW images. Optionally the manufacturing test includes testing the storage capability of the I/O device. The techniques further include an SSD manufacturing self-test capability.

Abstract: Methods and structure for determining compatibility between a pair of SAS devices for support of super-standard features of the devices. Features and aspects hereof provide for exchange of information between a first and second SAS device using SAS protocol in non-standard manners. The exchanges are designed to exchange information between compatible, enhanced device without causing protocol violation errors in either the first or second devices. The information exchanged represents super-standard features supported by each device. Mutually supported super-standard features are enabled for further communications between the devices. If no super-standard features are mutually supported or if the second device is non-enhanced, no super-standard features are enabled in further communications between the devices.

Abstract: An error detection device and method for a programming language is provided, the device including a program preparation unit configured to prepare a program by using a programming language, a logic converter configured to convert the prepared program to a sequence, a hash code calculator configured to detect a same logic relative to a sequence by dividing the converted sequence to a minimum unit of a plurality of program languages, calculating each hash code by the divided minimum unit of the plurality of program languages and comparing each calculated hash code, and an LCS (Longest Common Subsequence) calculator calculating an LCS relative to the sequence divided by the minimum unit of the plurality of program languages, and detecting a similar logic relative to the sequence by applying the calculated LCS to an LCS algorithm

Abstract: Aspects of the disclosure pertain to a system and method for providing dynamic y-buffer size adjustment for retained sector reprocessing (RSR). The system and method implement dynamic y-buffer size adjustment for RSR for promoting improved Sector Failure Rate (SFR) performance of the system. The system is a read channel system.

Abstract: Methods of designing an integrated circuit and an apparatus for designing an integrated circuit are disclosed herein. In one embodiment, a method includes: (1) generating a block model of the integrated circuit according to a first timing budget, (2) developing a top level implementation of the integrated circuit according to the first timing budget, (3) determining a second timing budget for the integrated circuit based on the block model and (4) modifying the block model and the top level implementation employing the second timing budget to provide a progressive block model and a modified top level implementation.

Abstract: The invention may be embodied in a SAS expander with register bits within Phys associated with I/O devices. Setting and unsetting the register bit in the Phy associated with a particular physical or logical device allows I/O traffic to be blocked and unblocked, as desired, to the selected physical or logical devices. In a particular embodiment, when the register bit is set to a blocking state, an OPEN request that comes in on the SAS link is rejected using OPEN_REJECT (RETRY). Phy register bits may be provided for multiple different SAS protocols that can be controlled individually for each attached SAS device. The Phy register bit may also be used to reject only SAS connection requests that attempt to leave a particular SAS link.

Abstract: An apparatus comprises a first housing having a top surface and a bottom surface, a second housing having a top surface and a bottom surface, and one or more supports coupling the first housing to the second housing such that the first and second housings are electrically connected and the bottom surface of the first housing overlays the top surface of the second housing. The one or more supports are configurable in at least a first configuration wherein the bottom surface of the first housing and the top surface of the second housing are substantially contiguous with one another and a second configuration wherein the bottom surface of the first housing and the top surface of the second housing are separated by a space.

Abstract: Disclosed is a method of synchronizing a plurality of processors accesses to at least one shared resource. One of a plurality of processors requests an exclusive region lock for a shared resource using a logical block address (LBA) of a dummy target. The LBA is defined in a region map that associates LBAs to shared resources. The exclusive region lock request is inserted as a node in a region lock tree of the dummy target. Access to the shared resource is granted based on a determination whether there is an existing region lock in the region lock tree that is overlaps with the new exclusive region lock request.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols.

Abstract: Various embodiments of the present invention provide systems and methods for data processing using variable scaling.

Abstract: An apparatus having a first cache and a controller is disclosed. The first cache may be configured to assert a first signal after receiving given information in response to being ready to receive additional information. The controller may be configured to (i) fetch the given information from a memory to the first cache and (ii) prefetch first information in a direct memory access transfer from the memory to the first cache in response to the assertion of the first signal.

Abstract: A first Network Interface Controller operates in a low power mode. The first Network Interface Controller transitions from low power mode to a power-up sequence if a sleep packet in not received from a second Network Interface Controller at the first Network Interface Controller within a predetermined time threshold.

Abstract: Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a second of the plurality of taps uses a second subset of the series of detected bits. The first subset of the detected bits includes one more bit than the second subset of the detected bits.

Abstract: Various embodiments of the present invention provide systems and methods for reduced clock rate data processing. As an example, a circuit is disclosed that includes a matched filter bank that receives a series of symbols at a rate corresponding to a sample clock. The matched filter bank includes a first matched filter tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and a second matched filter tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence. The circuit further includes a detector circuit that processes a series of symbol proxies including the first symbol proxy and the second symbol proxy at a rate corresponding to a reduced rate clock. The reduced rate clock is the sample clock divided by a factor.

Abstract: An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured to determine a noise distribution associated with the plurality of memory cell blocks and generate a noise prediction, which is based upon the noise distribution, when a read operation for the plurality of memory cell blocks is issued. The collaborative filtering module is also configured to modify the signal utilizing the noise prediction to at least substantially remove noise from the signal.