Abstract: Methods and apparatus are provided for trellis-based modulation encoding. A signal is modulation encoded by encoding one or more blocks of the signal using one or more corresponding edges in a trellis, wherein each edge in the trellis has a corresponding bit pattern; selecting a winning path through the trellis based on at least one transition-based run-length constraint; and generating an encoded sequence using edges associated with the winning path. Exemplary trellis pruning techniques are also provided. The winning path through the trellis is selected by minimizing one or more modulation metrics.

Abstract: Provided are a transformer cooling apparatus and a transformer assembly including the same. The transformer cooling apparatus includes a first plate on which a transformer including a magnetic member and a coil is seated, a second plate disposed on a side of the first plate, the second plate being spaced apart from the first plate, and a coolant passage in which a coolant flows, the coolant passage being defined between the first plate and the second plate.

Abstract: Disclosed are an apparatus for diagnosing a relay contact of an electric vehicle and a method thereof. The method includes measuring a first voltage input from a high-voltage battery to an inverter; comparing the first voltage with a second voltage output through the high-voltage battery; identifying a detection time point of the first voltage when the first voltage is greater than the second voltage; and determining whether a high-voltage relay, which intermits an output voltage of the high-voltage battery, is malfunctioned based on the identified detection time point.

Abstract: A measurement circuit is provided for measuring the resistance of a variable resistance element biased with an external voltage supply. The measurement circuit includes an analog-to-digital converter (ADC) and a reference generator connected with the ADC. The ADC is operative to receive a reference voltage and a first voltage developed across the variable resistance element, and to generate a digital output signal indicative of a relationship between the first voltage and the reference voltage. The reference generator is operative to generate the reference voltage as a function of the external voltage supply.

Abstract: A current detecting mechanism according to this invention includes a direct current shunt having a plurality of resistor members with high resistivity to output an electric potential difference across the resistor members, proportional to a current flowing through an electric load side terminal, as a voltage signal, and a hall sensor assembly having a pair of magnetic cores installed to face each other with an air gap therebetween, and a hall sensor to output an output voltage according to a magnetic flux induced in proportion to a current flowing through a load side terminal, without being connected with the direct current shunt, of load side terminals.

Abstract: A facsimile apparatus includes a user interface operative to facilitate communications between the apparatus and at least one user application in operative communication with the apparatus, a network interface operative to facilitate communications between the apparatus and an analog communications network and an IP communications network. The apparatus further includes a controller connected to the user interface and network interface. The controller is operative in a first mode to communicate with the analog communications network using a first facsimile protocol and being operative in at least a second mode to communicate with the IP communications network using the first facsimile protocol and a voice band data protocol.

Abstract: A memory management apparatus includes a first controller adapted to receive an input data sequence including one or more data frames and operative: to separate each of the data frames into a payload data portion and a header portion; to store the payload data portion in at least one available memory location in a physical storage space; and to store in a logical storage space the header portion along with at least one associated index indicating where in the physical storage space the corresponding payload data portion resides. The apparatus further includes a second controller operative, as a function of a data read request, to access the physical storage space using the header portion and associated index from the logical storage space to retrieve the corresponding payload data portion and to combine the header portion with the payload data portion to generate a response to the data read request.

Abstract: An apparatus for testing a thyristor valve includes: a current source circuit that provides an electric current when a thyristor valve as a test target is turned on; a voltage source circuit that provides a reverse voltage or a forward voltage when the thyristor valve is turned off; and a first auxiliary valve provided between a connection point between the thyristor valve and the voltage source circuit and the current source circuit, and that insulates the current source circuit from the voltage source circuit to protect the current source circuit from a high voltage of the voltage source circuit.

Abstract: An electronic storage system includes a first cylindrical storage area. The first cylindrical storage area is configured to rotate about an axis. The first cylindrical storage area includes a first storage surface. The storage system further includes a first access head, configured to access information stored on the first storage surface, and a first head arm. The first access head is disposed on the first head arm. A corresponding method, cylindrical storage area, and head access assembly are also provided.

Abstract: Selective enablement of operating modes or features of a storage system via host transfer rate detection enables, in some situations, enhanced performance. For example, a Solid-State Disk (SSD) having a serial interface compatible with a particular serial interface standard selectively enables coalescing of status information for return to a host based on detecting a particular host transfer rate capability. Some hosts are not fully compliant with the particular standard, being unable to properly process the coalesced status information. The selective enablement disables status coalescing for a non-compliant host and enables status coalescing for at least some compliant hosts, without the SSD having prior knowledge of coupling to a noncompliant/compliant host. The SSD conservatively determines the host is non-compliant/compliant based on a negotiated speed of the serial interface, and selectively disables/enables status coalescing in response to the negotiated speed.

Abstract: A search sphere-based linear block decoder is provided. A received vector, v, is decoded by computing a syndrome vector, S, corresponding to the received vector, v; (S=vH); obtaining a set of all possible error vectors, e, corresponding to the computed syndrome vector, S, wherein the set of all possible error vectors, e, is obtained from a pre-computed error table and has a specified maximum number of bit errors; calculating a set of all possible received vectors, x, based on the received vector, v, and the set of all possible error vectors, e; determining a k-bit code-vector x that is closest to the received vector, v; and determining an n-bit data-vector, d, associated with the k-bit code-vector x. The pre-computed error table can be generated by multiplying all possible error vectors by a Syndrome Matrix, to obtain all possible syndrome vectors associated with all possible error vectors.

Abstract: Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing integrated circuits. A CDC circuit can be used in an IC design to add a desired delay to a given clock path or data path, and then replaced with another footprint compatible CDC circuit to increase or decrease the delay in the given clock or data path to meet one or more timing requirements and achieve timing closure without having to repeat placement, signal distribution network synthesis or routing steps.

Abstract: Various embodiments of the present invention provide systems and methods for evaluating and debugging a data decoder. For example, a data decoder circuit is discussed that includes an input memory, a data decoder operable to decode data from the input memory in one or more iterations, an output memory operable to store decoded data from the data decoder, and a test port operable to provide access to the input memory, the data decoder and the output memory.

Abstract: Disclosed is an input module of a programmable logic controller (PLC) capable of counting coefficient values of multiple channels. An input module of a PLC includes a plurality of detection units, a decision unit and a control unit. The plurality of detection units receives a pulse signal corresponding to each channel, applied from a load having a plurality of channels, detects rising and falling edges of the pulse signal, and transmits an output signal that is the detected result. The decision unit receives a plurality of output signals respectively transmitted from the plurality of detection units, detects edges of the plurality of channels, and transmits a detection signal that is the detected result. The control unit identifies the presence of occurrence of an interrupt using the detection signal transmitted from the decision unit and performs a counting process using the applied pulse signal when the interrupt occurs.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to automatically set a gain of a baseline wander correction loop to restore the low frequency content in the signal based upon a sample taken from a first point in a signal pathway of the first circuit.

Abstract: A method for caching data in a storage medium implementing tiered data structures may include storing a first portion of critical data at the instruction of a storage control module. The first portion of critical data may be separated into data having different priority levels based upon at least one data utilization characteristic associated with a file system implemented by the storage control module. The method may also include storing a second portion of data at the instruction of the storage control module. The second storage medium may have at least one performance, reliability, or security characteristic different from the first storage medium.

Abstract: An apparatus having first and second circuits is disclosed. The first circuit may be disposed on a first side of a bus and configured to store thresholds in a first memory. Each threshold generally represents a respective one of a plurality of regular bit patterns in first data. The first circuit may also be configured to generate second data by representing each respective first data as (i) an index to one of the thresholds and (ii) a difference between the one threshold and the respective first data. A width of the bus may be narrower than the respective first data. The second circuit may be disposed on a second side of the bus and configured to (i) store the thresholds and a plurality of items in a second memory and (ii) reconstruct the first data by adding the respective thresholds to the second data in response to the items.

Abstract: Methods and structure for determining compatibility between a pair of SAS devices for support of super-standard features of the devices. Features and aspects hereof provide for exchange of information between a first and second SAS device using SAS protocol in non-standard manners. The exchanges are designed to exchange information between compatible, enhanced device without causing protocol violation errors in either the first or second devices. The information exchanged represents super-standard features supported by each device. Mutually supported super-standard features are enabled for further communications between the devices. If no super-standard features are mutually supported or if the second device is non-enhanced, no super-standard features are enabled in further communications between the devices.

Abstract: A driver circuit for a laser diode or other optical source comprises a controllable termination for a transmission line coupled between the driver circuit and the optical source, with the controllable termination being switchable between at least first and second termination configurations. The transmission line comprises a first conductor coupled to a first terminal of the optical source and a second conductor coupled to a second terminal of the optical source, and the driver circuit comprises a first current source configured to drive the first conductor, and a second current source configured to drive the second conductor. By way of example, the first termination configuration may comprise an alternating current (AC) termination configuration and the second termination configuration may comprise a direct current (DC) termination configuration.

Abstract: Disclosed are a cooling system for an electric vehicle and a control method thereof. The electric vehicle equipped with electronic parts including an electric motor. The electric vehicle includes a motor control unit to control the electric motor, a main control unit to control the electronic parts and the motor control unit, a water pump to circulate a cooling water cooling the electronic parts, the motor control unit, and the main control unit, and a temperature sensor to detect a temperature for an operation of the water pump and output the temperature to the motor control unit. The motor control unit generates a control signal to operate or stop the water pump according to a detection result of the temperature sensor.