Patents Assigned to LSI
  • STORAGE PROCESSOR FOR EFFICIENT SCALING OF SOLID STATE STORAGE
    Publication number: 20130311696
    Abstract: An SSD controller with two SAS interfaces includes an internal switch or expander to allow the SSD controller to function as both an initiator and target. Data packets received through one of the SAS interfaces may be directed to solid state memory elements directly connected to the SSD controller, or to one or more devices connected to the other SAS interface.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Applicant: LSI Corporation
    Inventors: Gregory L. Huff, Robert E. Ober, Steven M. Emerson
  • SCAN CONTROLLER CONFIGURED TO CONTROL SIGNAL VALUES APPLIED TO SIGNAL LINES OF CIRCUIT CORE INPUT INTERFACE
    Publication number: 20130311843
    Abstract: An integrated circuit comprises a memory or other circuit core having an input interface and an output interface, scan circuitry comprising at least one scan chain having a plurality of scan cells, and additional circuitry associated with at least one of the input interface and the output interface and testable utilizing said at least one scan chain. The scan circuitry further comprises a scan controller configured to control signal values applied to one or more signal lines of the input interface in conjunction with testing of the additional circuitry utilizing said at least one scan chain. For example, the scan controller may control signal values applied to respective address input and write enable signal lines in a manner that ensures that data written to a memory in a write operation of a given memory cycle can be read from the memory in a read operation of a subsequent memory cycle.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Applicant: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Priyesh Kumar
  • Self-Calibrating Differential Current Circuit
    Publication number: 20130307518
    Abstract: In one embodiment, a constant-current generator is connected in series with a dependent (e.g., tail) device. A switched capacitor circuit connected to the gate of the dependent device is operated to (i) charge at least one capacitor of the switched capacitor circuit, (ii) use the at least one charged capacitor to adjust the gate voltage of the dependent device to drive the dependent current through the dependent device to be equal to the constant current through the constant-current generator, and (iii) direct the dependent and constant currents through source and sink current nodes.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Applicant: LSI CORPORATION
    Inventor: Abhishek Duggal
  • INVERTER-CHARGER COMBINED DEVICE FOR ELECTRIC VEHICLES AND METHOD THEREOF
    Publication number: 20130307333
    Abstract: Disclosed is an inverter-charger combined device for electric vehicles configured to drive a 3-phase motor by charging a high voltage battery in case of charging mode, and switching a power of the high voltage battery in case of operation mode, the device including a first power supply unit for supplying a power to drive a switching unit of the rectifier, and a second power supply unit for supplying a power to drive a switching unit of the inverter, where the first power supply unit and the second power supply unit are configured to independently supply a power.
    Type: Application
    Filed: May 14, 2013
    Publication date: November 21, 2013
    Applicant: LSIS CO., LTD.
    Inventors: Byung Woon JANG, Chun Suk YANG
  • MEMORY DEVICE HAVING CONTROL CIRCUITRY CONFIGURED FOR CLOCK-BASED WRITE SELF-TIME TRACKING
    Publication number: 20130308398
    Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry comprises a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch.
    Type: Application
    Filed: May 17, 2012
    Publication date: November 21, 2013
    Applicant: LSI Corporation
    Inventors: Shailendra Sharad, Manish Umedlal Patel, Diwakar Ramadasu, Setti Shanmukheswara Rao
  • Methods and structure for storing errors for error recovery in a hardware controller
    Patent number: 8589722
    Abstract: Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: November 19, 2013
    Assignee: LSI Corporation
    Inventors: Joshua P. Sinykin, Sreedeepti Reddy, Jeffrey K. Whitt
  • Dual zone lighting apparatus
    Patent number: 8585238
    Abstract: A lighting apparatus comprising a first lighting assembly comprising at least one lower light source configured to cast light over at least a near field and a second lighting assembly comprising at least one upper light source configured to cast light over at least a far field, the second lighting assembly mounted above the first lighting assembly.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 19, 2013
    Assignee: LSI Industries, Inc.
    Inventor: Mark James Krogman
  • Multi-stage interconnection networks having smaller memory requirements
    Patent number: 8588223
    Abstract: In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 19, 2013
    Assignee: LSI Corporation
    Inventor: Kiran Gunnam
  • Adaptation of crossing latch threshold
    Patent number: 8588290
    Abstract: An apparatus including a bang-bang clock and data recovery module and a decision feedback equalizer. The decision feedback equalizer is coupled with the bang-bang clock and data recovery module. The apparatus is configured to reduce an effect on a settling point of the bang-bang clock and data recovery module due to coupling between the bang-bang clock and data recovery module and the decision feedback equalizer.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: November 19, 2013
    Assignee: LSI Corporation
    Inventor: Lizhi Zhong
  • Memory device having multi-port memory cell with expandable port configuration
    Patent number: 8588004
    Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least one of the memory cells comprises a pair of cross-coupled inverters, and a plurality of ports, including at least one write port. A given write port comprises at least one drive control circuit having an output coupled to respective gate terminals of both a write assist transistor and a drive transistor, with the write assist transistor being arranged in series with one of a pull-up and a pull-down path of a corresponding one of the inverters, and the drive transistor being configured to hold one of the internal nodes at a designated logic level in conjunction with a write operation. First and second drive control circuits of this type may generate complementary control signals for application to respective pairs of write assist and drive transistors associated with respective ones of the inverters.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: November 19, 2013
    Assignee: LSI Corporation
    Inventors: Md Rahim Chand Sk, Nikhil Lad
  • Static memory with segmented clear
    Patent number: 8588024
    Abstract: A static memory system with multiple memory cell that, in response to a reset signal, simultaneously resets or clears a segment of the memory cells in the memory. Clearing the entire memory or a portion thereof is accomplished by sequencing though a subset of address bits while asserting the reset signal.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: November 19, 2013
    Assignee: LSI Corporation
    Inventors: Manish Umedlal Patel, Vikash
  • Methods and structure for hardware management of serial advanced technology attachment (SATA) DMA non-zero offsets in a serial attached SCSI (SAS) expander
    Patent number: 8589607
    Abstract: Methods and structure for enhanced SAS expander functionality to store and forward buffered information transmitted from a SATA end device to an STP initiator device while managing use of Non-Zero Offset (“NZO”) field values in DMA Setup FISs transmitted by the SATA end device. The enhanced expander establishes a connection between an STP initiator and a SATA end device. The expander forwards a read command from the initiator to the end device. If NZO use is supported and enabled in the end device, the end device may return read data in any order by use of the NZO field values in multiple DMA Setup FISs. The expander is further adapted to store received data and the associated multiple DMA Setup FISs from the end device in its buffer and forwards the stored data to the initiator device. In another embodiment, use of NZO in the end device is disabled.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: November 19, 2013
    Assignee: LSI Corporation
    Inventor: Gurvinder Pal Singh
  • Total power optimization for a logic integrated circuit
    Patent number: 8589853
    Abstract: A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: November 19, 2013
    Assignee: LSI Corporation
    Inventors: Benjamin Mbouombouo, Ramnath Venkatraman, Ruggero Castagnetti
  • Methods and apparatus for synchronization mark detection based on a position of an extreme distance metric
    Patent number: 8587888
    Abstract: Methods and apparatus are provided for detection of a synchronization mark based on a position of an extreme distance metric. A synchronization mark is detected in a received signal by computing a distance metric between the received signal and an ideal version of the received signal expected when reading the synchronization mark, wherein the distance metric is computed for a plurality of positions within a search window; determining a substantially extreme distance metric within the search window; and detecting the synchronization mark based on a position of the substantially extreme distance metric. The distance metric can comprise a sum of square differences or a Euclidean distance between the received signal and the ideal version of the received signal.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 19, 2013
    Assignee: LSI Corporation
    Inventors: Erich F. Haratsch, Shaohua Yang, Nenad Miladinovic, Yuan Xing Lee
  • MULTI-PASS ROUTING TO REDUCE CROSSTALK
    Publication number: 20130305203
    Abstract: An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 14, 2013
    Applicant: LSI CORPORATION
    Inventor: Anuj Soni
  • SIGNAL COUPLING APPARATUS FOR POWER LINE COMMUNICATION
    Publication number: 20130300208
    Abstract: Disclosed is a signal coupling apparatus for power line communication, the apparatus comprising a housing centrally formed with a groove to pass a power line there through, and a non-contact interface unit accommodated inside the housing to induce a power signal or a power line communication signal from the power line using an electromagnetic induction.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 14, 2013
    Applicant: LSIS CO., LTD.
    Inventors: Young Gyu YU, Jae Kang SIM
  • METHODS AND STRUCTURE FOR IMPROVED AND DYNAMIC ZONING IN SERIAL ATTACHED SCSI EXPANDERS
    Publication number: 20130304951
    Abstract: Methods and structure for dynamically modifying SAS Zoning Features of a SAS expander based on present operating status of the expander. Rules are provided and interpreted within the expander to define changes to be made to the present SAS Zoning Features based on changes to the present operating status of the expander. The present operating status may be, for example, the present day, date, time of day, etc. Exemplary rules may define a modification to the zone group identifier to be associated with a PHY of the expander based on the present operating status of the expander. Exemplary rules may also define a modification to the zone permission defined for a pair of zone group identifiers. Further features and aspects hereof provide for a read-only zone permission value in addition the standards of the SAS specification.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 14, 2013
    Applicant: LSI CORPORATION
    Inventors: Ankit Goel, Abhijit Suhas Aphale, Manjusha Gopakumar
  • MOTOR CONTROL APPARATUS AND METHOD OF CONTROLLING DRIVING OF MOTOR BY MOTOR CONTROL APPARATUS
    Publication number: 20130299267
    Abstract: Disclosed are a motor control apparatus and a method of controlling driving of a motor by the motor control apparatus, in which the motor control apparatus, which controls an electrically-driven motor, autonomously detects vehicle collision to autonomously control the operating state of the motor. The method includes determining a collision state of a vehicle, and stopping the driving of the motor according to the collision state of the vehicle.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 14, 2013
    Applicant: LSIS CO., LTD.
    Inventor: Duk Yun CHO
  • METHODS AND STRUCTURE FOR CONFIGURING A SERIAL ATTACHED SCSI DOMAIN VIA A UNIVERSAL SERIAL BUS INTERFACE OF A SERIAL ATTACHED SCSI EXPANDER
    Publication number: 20130304952
    Abstract: Methods and structure are provided for managing a Serial Attached SCSI (SAS) domain via Universal Serial Bus (USB) communications. The system comprises a SAS expander. The SAS expander comprises a plurality of physical links, a USB interface, and a control unit. The control unit is operable to receive USB packets via the USB interface, to determine SAS management information based upon the received USB packets, and to alter a configuration of the SAS domain based upon the SAS management information determined from the USB packets.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 14, 2013
    Applicant: LSI CORPORATION
    Inventors: Kaushalender Aggarwal, Mandar Joshi, Saurabh B. Khanvilkar, Rakesh Verma
  • Lighting
    Patent number: D693959
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 19, 2013
    Assignee: LSI Industries, Inc.
    Inventors: John D. Boyer, Earl G. Boertlein, II, Rob Allen Rooms