Abstract: Various embodiments of the present invention provide systems and methods for data filter tuning. As an example, a method for filter tuning is disclosed that includes: providing a tunable filter having an operation filter and a calibration filter; applying a low frequency test input to the operation filter in place of an input signal to yield a first filter output; calculating a low frequency magnitude value corresponding to the first filter output; applying a high frequency test input to the operation filter in place of an input signal to yield a second filter output; calculating a high frequency magnitude value corresponding to the second filter output; modifying a tuning factor of the calibration filter when a ratio of the high frequency magnitude value and the low frequency magnitude value is outside of a defined range; and storing the tuning factor of the calibration filter when the ratio of the high frequency magnitude value and the low frequency magnitude value is within the defined range.

Abstract: Methods and systems for executing a decompressed portion of an option memory in a shadow memory. An area of system memory is allocated and a portion of the option memory is decompressed using the allocated area. The decompressed portion is stored in the shadow memory so the decompressed portion can be executed in shadow memory.

Abstract: A transceiver apparatus includes a process, a first type of transceiver circuit for data transmission, a second type of transceiver circuit for data transmission, and a communications interface for communicating between the first type of transceiver circuit and an external device. The first type of transceiver circuit is co-located with a physical layer associated with the first type of transceiver circuit. In some embodiments, the first type of transceiver circuit can be, for example, a USB 2.0 transceiver circuit, and the second type of transceiver circuit can be a USB 3.0 transceiver circuit. The aforementioned external device can be an external USB device.

Abstract: Techniques are disclosed for asynchronous calibration for eye diagram generation. For example, a method for calibrating a process for generating a data eye associated with a received signal comprises the following steps. Samples of the received signal are obtained for a first unit interval using a first data latch and a roaming latch. A delay offset is determined between the first data latch and the roaming latch by comparing at least one sample obtained using the first data latch and at least one sample obtained using the roaming latch, wherein the delay offset determined by the comparison is used to calibrate the process for generating the data eye associated with the received signal. A similar comparison may be done for a second data latch and used to calibrate the process. The method is able to find the accurate position of each data latch with respect to the roaming latch so as to improve the accuracy of data decoding in a digital receiver, i.e., provide receiver optimization.

Abstract: Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains.

Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output.

Abstract: An apparatus for determining the presence of a tone in an input signal includes memory circuitry and data processing circuitry coupled to the memory circuitry. The data processing circuitry is operative to receive multiple samples of the input signal, and to determine a first value at least in part by multiplying each of the samples by respective ones of a first set of values for an impulse response and summing the results. The data processing system is also operative to determine a second value at least in part by multiplying each of a portion of the samples by respective ones of a second set of values for the impulse response and summing the results. The data processing system is operative to determine the power of the tone in the multiple samples of the input signal at least in part by utilizing the first value and the second value.

Abstract: A power measurement cell, or group of power measurement cells, for the calculation of the power consumption of one or more electrical signals, as well as monitoring electrical signals in an integrated circuit, are disclosed. Further, super cells for the automation of specialized functions associated with the calculation of power consumption of one or more electrical signals are also disclosed. Methods associated with the use of the one or more power measurement cells and for the use of super cells for the calculation of the power consumption of one or more electrical signals are also described.

Abstract: A digital protective relay includes at least one daughter PCB having an electronic circuit which generates electromagnetic interference noise or high frequency noise; and a backplane printed circuit board having, on an upper surface thereof, a plurality of first connectors for connection with the daughter PCB, connected to the daughter PCB through the first connectors, and providing a noise discharge path along which the electromagnetic interference noise or the high frequency noise from the daughter PCB flows to an external ground.

Abstract: Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a lighting component and a mounting structure. The lighting component can include a light source, a plate, and a frame. The light source can include one or more lighting elements, such as light emitting diodes. The lighting component can be releasably secured to the mounting structure.

Abstract: Devices and systems for tool-less assembly of cable chains that are capable of being retractably stored. The device comprises a first contact element, a second contact element, and a lengthwise member. The first contact element is adapted for movable contact with a receiving member of a first cable chain segment. The second contact element is adapted for movable contact with a receiving member of a second cable chain segment. The lengthwise member is fixedly attached to the contact elements. When an angle between the first and the second cable chain segments is a first value, the lengthwise member experiences elastic deformation, generating a spring force at each contact element sufficient to pull the receiving member of the first cable chain segment rotatably towards the receiving member of the second cable chain segment, thereby reducing the angle between the first and the second cable chain segments to a second value.

Abstract: A method for manufacturing a sealed contact point is performed by injecting an arc extinguishing gas into an air-tight space of an electromagnetic switching device and sealing it. The method for manufacturing a sealed contactor, including: forming a driving body and coupling a housing and a plate; air-tightly fixing a detachable chamber and forming the interior of the chamber under an insulating gas atmosphere; tightly attaching the cylinder to the plate by a tight-attachment inducing member within the chamber under the insulating gas atmosphere to form a sealing structure; exhausting the chamber; disassembling the chamber from the plate; and sealing the tightly attached plate and the cylinder.

Abstract: A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2N data locations and K spare locations. At least one page in the memory has 2M user data sectors and each sector has 2N-M+L locations therein. Because L is at least 1 but less than 2N-M, user data is stored in the spare memory locations. By storing user data in spare locations that were previously off-limits to user data, enterprise-sized sectors can be efficiently stored in flash memories with little wasted memory, thereby making flash-memory systems compatible with existing hard-drive storage systems in enterprise system applications.

Abstract: In a communication receiver, timing recovery circuitry includes a loop filter associated with a timing recovery loop of a first communication device. The first communication device is in communication with a second communication device prior to a temporary power down/power up sequence in the first communication device. The loop filter is configured to: (i) temporarily disable at least a portion of the timing recovery loop after the temporary power down/power up sequence in the first communication device; and (ii) initiate a progression through a set of potential sampling phases to determine a given sampling phase at which the first communication device can recommence communication with the second communication device.

Abstract: A system and method for storing variable width stack elements in a single memory stack is disclosed. In one example embodiment a first variable width stack element is split into one or more sub-elements. The width of the sub-elements may be less than or equal to a width of the single memory stack. A first memory pointer is created for providing an address of a first read pointer in the single memory stack. The first read pointer may provide an address corresponding to a first sub-element of the first variable width stack element. The first sub-element is written in a first available location in the single memory stack. A write pointer of the single memory stack is incremented when the first sub-element is written to the first available location on the single memory stack. The steps of writing and incrementing are repeated for a next sub-element until all of the sub-elements are stored in the single memory stack.

Abstract: A layered decoder that uses a non-standard schedule, where a non-standard schedule is a schedule where the frequency of one or more layers in the schedule is greater than one. When the layered decoder converges on a near codeword using an initial schedule, the layered decoder identifies the layer Lmaxb of the near codeword, which layer contains the greatest number of unsatisfied check nodes, and selects a subsequent non-standard schedule from a schedule set. The non-standard schedules in the schedule set are sorted by key layer, where the key layer is a layer that appears in the non-standard schedule with the greatest frequency. The layer decoder selects a non-standard schedule from the schedule set where the key layer of selected non-standard schedule is equal to the identified Lmaxb value.

Abstract: A data processing system comprises data processing circuitry, a cache memory, and memory access circuitry. The memory access circuitry is operative to assign a memory address region to be allocated in the cache memory with a predefined initialization value. Subsequently, a portion of the cache memory is allocated to the assigned memory address region only after the data processing circuitry first attempts to perform a memory access on a memory address within the assigned memory address region. The allocated portion of the cache memory is then initialized with the predefined initialization value.