Abstract: Provided is a relay dualization apparatus, in a substation automation system including at least one or more upper units and at least one or more lower units, the apparatus including a plurality of first relays receiving a power data from the lower unit using a predetermined communication method, and transmitting the power data to the upper unit, and receiving a control command from the upper unit and transmitting the control command to the lower unit, and a second relay performing communications with the plurality of first relays using the communication method to replace a relay that has generated an error in the plurality of relays.

Abstract: A data storage system includes at least one host device configured to initiate a data request, at least one target device configured to store data, and a serial attached SCSI (SAS) switch coupled between the at least one host device and the at least one target device. The SAS switch includes a cache memory and includes control programming configured to determine whether data of the data request is stored in the cache is at least one of data stored in the cache memory of the SAS switch or data to be written in the cache memory of the SAS switch. The cache memory of the SAS switch is a shared cache that is shared across each of the at least one host device and the at least one target device.

Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a lighting component and a mounting structure. The lighting component can include a light source, a plate, and a frame. The light source can include one or more lighting elements, such as light emitting diodes. The lighting component can be releasably secured to the mounting structure.

Abstract: Various embodiments of the present invention provide systems and methods for event alignment control. For example, an event alignment control circuit is disclosed that includes a delay table, a flag write controller circuit, and a signal reconstruction circuit. The delay table includes at least a first register and a last register, and is operable to transfer data from the first register to the last register. The flag write controller circuit is operable to receive an indication of assertion of an event flag and to write information relevant to the event flag to the first register of the delay table. The signal reconstruction circuit is electrically coupled to the last register, and reconstructs the event flag based at least in part on the information relevant to the event flag obtained from the last register.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a light source, a plate, and frame. The light source can include one or more lighting elements that are in thermal communication with the light source. The plate can have a dissipative portion extending outward from a point of thermal communication between the plate and the light source. The frame can at least partially enclose the light source and may also be in thermal communication therewith.

Abstract: The present invention is a system for implementing a meta-disk aggregation model for storage controllers. The system includes a storage controller configured for communicatively coupling with a server. The system further includes a meta-disk drive group having a plurality of disk drives, the meta-disk drive group configured for being communicatively coupled with the storage controller, each of the plurality of disk drives including a drive interface connector. Additionally, each drive interface connector of the plurality of disk drives of the meta-disk drive group is configured for being communicatively coupled to each of the remaining drive interface connectors of the plurality of disk drives, thereby allowing the plurality of disk drives to communicate as a single device with the storage controller.

Abstract: A message tracking and verifying system for verifying the correctness of messages being passed may comprise a tracking module for tracking a request message and a verifying module for verifying a response message. The tracking module may be configured to store a calculated source address and a calculated response address range. The verifying module may be configured to obtain an actual source address from the response message and an actual response address range for the response message. The correctness of the response message is determined based on the comparison of the calculated source address with the actual source address and the comparison of the calculated response address range with the actual response address range.

Abstract: A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.

Abstract: A method for metadata management in a storage system configured for supporting sub-LUN tiering. The method may comprise providing a metadata queue of a specific size; determining whether the metadata for a particular sub-LUN is cached in the metadata queue; updating the metadata for the particular sub-LUN when the metadata for the particular sub-LUN is cached in the metadata queue; inserting the metadata for the particular sub-LUN to the metadata queue when the metadata queue is not full and the metadata is not cached; replacing an entry in the metadata queue with the metadata for the particular sub-LUN when the metadata queue is full and the metadata is not cached; and identifying at least one frequently accessed sub-LUN for moving to a higher performing tier in the storage system, the at least one frequently accessed sub-LUN being identified based on the metadata cached in the metadata queue.

Abstract: Methods and apparatus are provided for wireless channel estimation using interpolation elimination in the Eigen domain. Channel components at known OFDM symbol locations are interpolated to other OFDM symbol locations. Methods and apparatus are provided for interpolating in the Eigen domain between reference signals (i.e., training signals) to estimate the equalizer coefficients with a reduced complexity. In particular, one aspect of the present invention performs the required interpolation before a required matrix inversion in the Eigen domain.

Abstract: Various embodiments of the present invention provide systems and methods for medium utilization control. As an example, a method for identifying potentially damaged media regions is discussed that includes receiving a data set; performing a data detection process on the data set to yield a detected output and a status value corresponding to the data set; performing a data decoding process on the detected output to yield a decoded output; and identifying a region of a storage medium from which the data set was derived as failing based at least in part on the status value.

Abstract: A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe indicating when to sample data on a second memory lane of the electronic memory. The method may also include determining a fourth delay value for the second memory lane of the electronic memory utilizing the third delay value and the determined difference between the first delay value and the second delay value.

Abstract: A method for reducing the size of a DFA associated with a regular expression separates the functions of locating subexpressions within the DFA and determining if the located subexpressions satisfy a regular expression. For example, the functions of (1) locating subexpressions in a range asserting expression and, (2) determining whether the subexpressions satisfy the range of the range asserting expression are partitioned. In one embodiment, a first component may locate the subexpressions in a data stream using one or more DFAs, while a second component determines if the located subexpressions satisfy the range. In this embodiment, because the DFAs are not configured to determine a relationship between subexpressions, such as a range between subexpressions, the size of the resultant DFA may be significantly reduced.

Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

Abstract: A solid insulated switchgear having at least one circuit switches for switching a three-pole AC circuit includes a plurality of bus-bars for pole. Each of the bus-bars for pole being providing correspondingly for each pole comprises a ring-shaped bus-bar portion electrically connecting the arc extinguishing mechanisms for the same pole, and each having an internal electrical conductor portion and an external solid insulated mold portion in which the conductor portion is built; and a plurality of extended connecting portions respectively extended from the ring-shaped bus-bar portion while being space apart from one another in a circumferential direction so that the plurality of circuit switches are connected in the state in which the plurality of circuit switches are separated from one another.

Abstract: Provided is a PLC network extension system, the system including a basic base generating a control data for controlling a plurality of extension bases, generating a network frame using the control data, and transmitting the network frame to one extension base in the plurality of extension bases via a network cable, and the plurality of extension bases extracting a control data from the received network frame to control a pre-installed module based on the control data.

Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.

Abstract: Luminaires are disclosed that include refractive and/or reflective structures that can provide or distribute lighting for a given area with high uniformity and efficiency. The structures can be used to distribute light from one or more light sources for lighting target areas with a desired light distribution. The lighting structures can be included in light strips or luminaires. Such luminaire can be utilized in place of fluorescent lights and can facilitate quick and easy retrofit for previous fluorescent lighting applications. The disclosed techniques and systems (including components and structures) can be particularly useful when employing one or more LEDs as light sources.

Abstract: Provided is a heat sinking plate, the plate formed with a square-shaped opening of a predetermined length when viewed from the other direction of a rectangular metal plate by erecting four triangles obtained by diagonally and crossly cutting a square of a predetermined length to one direction of the metal plate at a predetermined first angle relative to the metal plate.