Patents Assigned to LSI
  • Publication number: 20130066441
    Abstract: Provided are a PLC device and a method for controlling the same. The method includes: receiving input data from an external; storing the received input data in an input area of a data input/output unit; reading the input data from the input area of the data input/output unit in order to perform a calculation operation; storing output data, which is a result of the calculation operation, in an output area of the data input/output unit; and transmitting the output data in the output area of the data input/output unit to an output circuit.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 14, 2013
    Applicant: LSIS CO., LTD.
    Inventor: Jo Dong PARK
  • Publication number: 20130067251
    Abstract: A relay and a data processing method are provided. The relay includes: a detection unit for classifying and detecting event oriented monitoring data and non-event oriented monitoring data from monitoring data; a storage unit for storing the detected monitoring data; a communication unit for receiving a request signal of the monitoring data from a monitoring device and transmitting corresponding monitoring data in response to a transmission request signal of the monitoring data; and a control unit for extracting event oriented monitoring data from the monitoring data and performing a control to transmit the monitoring data requested from the monitoring device.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 14, 2013
    Applicant: LSIS CO., LTD.
    Inventor: BYUNG JOON JEON
  • Patent number: 8396985
    Abstract: Described embodiments provide a network processor that includes a security sub-processor to prevent replay attacks on the network processor. A memory stores an anti-replay window corresponding to a data stream of the network processor. The anti-replay window has N bits initialized to correspond to data packet sequence numbers in the range 1 to N. The anti-replay memory is stored in a plurality of data words. A plurality of flip-flops store word valid bits corresponding to each of the data words. A multiplexer selects the word valid bit corresponding to a data word requested by the security processor, and an AND gate performs a bitwise AND operation between the selected data word and word valid bit. When the network processor receives a data packet, the security sub-processor determines a value of the received sequence number with respect to minimum and maximum values of a sequence number range of the anti-replay window.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: March 12, 2013
    Assignee: LSI Corporation
    Inventor: Ephrem Wu
  • Patent number: 8397025
    Abstract: A method and apparatus for determining a cache line in an N-way set associative cache are disclosed. In one example embodiment, a key associated with a cache line is obtained. A main hash is generated using a main hash function on the key. An auxiliary hash is generated using an auxiliary hash function on the key. A bucket in a main hash table residing in an external memory is determined using the main hash. An entry in a bucket in an auxiliary hash table residing in an internal memory is determined using the determined bucket and the auxiliary hash. The cache line in the main hash table is determined using the determined entry in the auxiliary hash table.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: March 12, 2013
    Assignee: LSI Corporation
    Inventors: Maghawan Punde, Deepak Lala
  • Patent number: 8397023
    Abstract: A system and method for handling IO to drives in a RAID system is described. In one embodiment, the method includes providing a multiple disk system with a predefined strip size. IO request with a logical block address is received for execution on the multiple disk system. A cache line size from a plurality of cache line sizes is allocated, based on the available memory for allocation to cache line. A plurality of sub-IO requests with a sub-strip size is generated, where the sub-strip size is smaller than the strip size, based on the allocated cache line size. The generated sub-IO commands are executed on the multiple disk system.
    Type: Grant
    Filed: December 18, 2010
    Date of Patent: March 12, 2013
    Assignee: LSI Corporation
    Inventors: Anant Baderdinni, Allen Kelton, Michael Richmond
  • Patent number: 8397184
    Abstract: A library cell is designed, and then the width of the polys is increased, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The method can be used in association with a 45 nm digital library cell. Specifically, a library cell having 40 nm polys is designed, and then the width of each of the polys is increased by 5 nm to 45 nm, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The poly lines and contacts can be shifted by starting at the center and going out radially, or by beginning at the perimeter and moving radially inward. The method can be used with any library cell design which is entirely GDS based, including, for example, 32 nm library cell design.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: March 12, 2013
    Assignee: LSI Corporation
    Inventor: Richard Schultz
  • Patent number: 8397196
    Abstract: A computer-executed method for designing dummy metal object locations in an integrated circuit design. The method comprises the steps of: a) receiving an integrated circuit design as input; b) finding areas of the integrated circuit design that do not meet a minimum metal density requirement; c) finding areas of the integrated circuit design having a critical timing path; d) blocking empty routing tracks that are adjacent to critical nets of the critical timing paths located in step (c), for prospective dummy metal object placement for the areas commonly located in both of steps (b) and (c); and e) placing a minimum number of dummy metal objects in empty tracks such that the minimum metal density requirement is met for the areas that were found in step (b), but were not blocked in step (d).
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: March 12, 2013
    Assignee: LSI Corporation
    Inventor: Alexander Tetelbaum
  • Patent number: 8397143
    Abstract: An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to calculate a plurality of preliminary syndromes from a plurality of received symbols. The second circuit may be configured to calculate a plurality of normal syndromes by modifying the preliminary syndromes using at most two Galois Field multiplications. The third circuit is generally configured to calculate an errata polynomial based on the normal syndromes.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: March 12, 2013
    Assignee: LSI Corporation
    Inventors: Ilya V. Neznanov, Elyar E. Gasanov, Pavel A. Panteleev, Pavel A. Aliseychik, Andrey P. Sokolov
  • Publication number: 20130057435
    Abstract: Provided is an auxiliary Access Point (AP) tag and a positioning system using the same, wherein the auxiliary AP tag simpler in structure than a conventional AP is arranged at the system to be provided with only a function of transmitting an identifier (e.g., a service set identifier), whereby position accuracy can be stably obtained and cost can be reduced.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 7, 2013
    Applicant: LSIS CO., LTD.
    Inventor: Bum Youl KIM
  • Publication number: 20130057338
    Abstract: A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 7, 2013
    Applicant: LSI Corporation
    Inventors: Ramnath Venkatraman, Shashidhara S. Bapat, Ruggero Castagnetti
  • Publication number: 20130061107
    Abstract: Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding. For example, in one embodiment an apparatus includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The check node processor includes a min finder circuit operable to identify a minimum, a next minimum and an index of minimum value in the variable node to check node messages. The variable node processor and check node processor are operable to perform layered multi-level decoding.
    Type: Application
    Filed: November 18, 2011
    Publication date: March 7, 2013
    Applicant: LSI Corporation
    Inventors: Chung-Li Wang, Zongwang Li, Lei Chen, Johnson Yen
  • Publication number: 20130061029
    Abstract: The present invention is directed to a boot appliance for a data storage system. The boot appliance is a self-contained, pre-configured device that serves as a boot device for multiple servers. The boot appliance contains multiple hard drives which are configured into one or more RAID volumes. Each volume is divided into multiple partitions, with each partition serving as the boot drive for any server connected to it. The boot appliance provides its own environmental controls and Ethernet connection which may be used for providing alerts regarding the health of the components of the boot appliance and/or data storage system to a monitoring system, such as a network management system. The boot appliance may provide a boot drive and operating system image to multiple servers at the same time.
    Type: Application
    Filed: December 2, 2011
    Publication date: March 7, 2013
    Applicant: LSI CORPORATION
    Inventors: Gregory L. Huff, Timothy E. Hoglund, Brad D. Besmer, Mark J. Jander, Edward F. Marchand, Jason C. McGinley
  • Patent number: 8390406
    Abstract: A mold cased circuit breaker, which includes a casing, a switching unit disposed in the casing to open or close an electric circuit, and movable and stationary contactor units present within the casing, includes an arc-extinguishing unit. The arc-extinguishing unit includes a pair of side plates facing each other with being spaced from each other, at least one first grid arranged between the side plates and spaced apart from one another with preset intervals, and a second grid coupled to upper ends of the side plates, spaced apart from the first grid, and having a bent portion with a preset angle.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: March 5, 2013
    Assignee: LSIS Co., Ltd.
    Inventor: Young Gyu An
  • Patent number: 8387871
    Abstract: A tamper pool RFID tag apparatus, system and method for keying the RFID tag in association with an object. An oscillator circuit configured on an RFID tag substrate enables the RFID tag to be keyed with respect to the object. One or more capacitors that are operatively connected in association with the RFID tag substrate via a substrate vias determine an oscillator frequency pulse when placed on the object. A comparator compares the oscillator frequency pulse with a predetermined pulse count stored in a latch/storing unit. The RFID tag circuit can accept the object in, for example, a vending machine, if the frequency pulse matches the predetermined pulse count in order to effectively handle object returns in a wide range of commercial applications.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: March 5, 2013
    Assignee: LSI Corporation
    Inventor: Roger A. Fratti
  • Patent number: 8392692
    Abstract: In one embodiment, the present invention determines index values corresponding to bits of a binary vector that have a value of 1. During each clock cycle, a masking technique is applied to M sub-vector index values, where each sub-vector index value corresponds to a different bit of a sub-vector of the binary vector. The masking technique is applied such that (i) the sub-vector index values that correspond to bits having a value of 0 are zeroed out and (ii) the sub-vector index values that correspond to the bits having a value of 1 are left unchanged. The masked sub-vector index values are sorted, and index values are calculated based on the masked sub-vector index values. The index values generated are then distributed uniformly to a number M of index memories such that the M index memories store substantially the same number of index values.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: March 5, 2013
    Assignee: LSI Corporation
    Inventor: Kiran Gunnam
  • Patent number: 8392654
    Abstract: A method for a redundant array of independent disks (RAID) controller for migrating a RAID level in spanned arrays is disclosed. In one embodiment, a method for a RAID controller for migrating a RAID level in spanned arrays includes receiving a command for a RAID level migration from a first RAID level in spanned arrays to a second RAID level. The method further includes initializing a number of pointers which correspond to a number of the spanned arrays in the first RAID level, and transferring at least one data block of the first RAID level in the spanned arrays using the number of pointers to form the second RAID level.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: March 5, 2013
    Assignee: LSI Corporation
    Inventors: Priyadarshini Mallikarjun Sidnal, Gururaj Shivashankar Morabad
  • Patent number: 8388166
    Abstract: Lighting apparatus and structures are described to space electrical drivers from a light panel. In this way, a driver box housing the driver can be spaced from the light panel to communicate with pre-existing facilities (e.g. electrical wiring) and can serve the additional advantage of keeping the driver box out of standing water that may accumulate on the structure.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: March 5, 2013
    Assignee: LSI Industries, Inc.
    Inventors: Rob Allen Rooms, John D. Boyer
  • Publication number: 20130049799
    Abstract: A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.
    Type: Application
    Filed: October 30, 2012
    Publication date: February 28, 2013
    Applicant: LSI CORPORATION
    Inventor: LSI Corporation
  • Publication number: 20130051016
    Abstract: A reflector assembly for a lighting apparatus, the reflector assembly comprising two or more reflector modules configured for associating with one or more light sources, each reflector module comprising one or more reflectors for being located adjacent to alight source when the reflector module is associated with the one or more light sources, the one or more reflectors configured to reflect light from the adjacent light source. The reflector modules may further comprising a cover plate defining a plurality of light source apertures for allowing a light source to protrude through the cover plate, at least a first of the one or more light source apertures disposed adjacent to an overhead reflector and at least a second of the one or more light source apertures disposed adjacent to a lateral reflector. The reflector assembly can comprising any number of reflector modules and the reflector modules can be arranged in different configurations to create different light distributions with the same reflector modules.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: LSI Industries, Inc.
    Inventors: John D. Boyer, James G. Vanden Eynden, Larry A. Akers
  • Publication number: 20130050955
    Abstract: Apparatus and systems for improved access to storage devices from the sides of sleds mounted in storage enclosures. Embodiments provide apparatus and systems for a sled in a storage enclosure that provides access to storage devices on either side of the sled when the sled is slid forward out of its enclosure. Multiple sleds may be enclosed within a single enclosure to permit access to a portion of the storage devices in the enclosure hence reducing the problems of instability of the rack if the enclosure is mounted near the top of the rack.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: LSI CORPORATION
    Inventors: Macen Shinsato, Mohamad H. El-Batal, Robert E. Stubbs, Jason M. Stuhlsatz, John R. Kloeppner