Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an increased iteration enable signal, a first detector circuit, a second detector circuit, and a data decoding circuit. The first detector circuit receives a data set and performs a data detection on the data set to provide a detected data set. The data decoding circuit receives a derivative of the detected data set and performs a decoding process to provide a decoded data set. The decoded data set is provided to the second detector circuit based at least in part on an assertion level of the increased iteration enable signal.

Abstract: A communication device comprises a signal combiner, first storage elements, second storage elements and a controller. The signal combiner is configured to combine overhead information with additional information in forming a frame of a signal. The first storage elements are adapted to receive respective portions of a given block of the overhead information to be applied to the signal combiner, and the second storage elements are coupled between respective ones of the first storage elements and respective inputs of the signal combiner. The controller is operative to monitor a count of portions of the frame as the frame is formed by the signal combiner and to control loading of the portions of the given block of the overhead information into the second storage elements from the first storage elements responsive to the monitored count.

Abstract: Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes a first detector, a second detector, a decoder and a unified memory buffer. An input data set is received by the first detector that performs a data detection and provides a first detected data set. The decoder receives a derivative of the first detected data set and performs a decoding operation that yields a decoded data set. In some cases, the derivative of the first detected data set is an interleaved version of the first detected data set. The decoded data set is written to a unified memory buffer. The first decoded data set is retrievable from the unified memory buffer and a derivative thereof is provided to the second detector. In some cases, the derivative of the decoded is a de-interleaved version of the decoded data set.

Abstract: A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2N data locations and K spare locations. At least one page in the memory has 2M?1 user data sectors and each sector has 2N-M+L locations therein. Error-correction code (ECC) data related to the user data is calculated and stored in at least the 2M user data locations unused by the 2M?1 user data sectors. Because L is at least 1 but less than 2N-M (N>M), at least a portion of one user data sector is stored in the spare memory locations. Additional locations in each page are available to allow for the ECC data to have additional redundancy bits added per sector, thereby making the flash memory system more robust and reliable.

Abstract: A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

Abstract: Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.

Abstract: A method for implementing motion estimation comprising the steps of (A) performing a motion estimation search on one or more blocks of sub-sampled images to generate a first plurality of motion vector scores, (B) applying a first adjustable bias to any one or more of said first plurality of motion vector scores with a lowest sum of absolute differences score, (C) selecting a motion vector with a lowest adjusted score in response to applying the first adjustable bias, (D) performing a motion estimation search on one or more blocks of non-sub-sampled images to generate a second plurality of motion vector scores with the selected motion vector with the lowest adjusted score, (E) applying a second adjustable bias to any one or more of the second plurality of motion vector scores with the lowest sum of absolute differences score and (F) selecting a final motion vector for each target block position.

Abstract: Various embodiments of the present invention provide systems, methods and circuits for memory utilization. As one example, a memory system is disclosed that includes a memory bank and a memory access controller circuit. The memory bank includes a number of default memory cells and a number of redundant memory cells. The memory access controller circuit is operable to access a usable memory space including both the combined default memory cells and the redundant memory cells.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes at least a first detector, a second detector, a decoder, and a queuing buffer. The first detector is operable to perform a data detection on an input data set at a first time. The decoder receives a derivation of an output from the first detector and performs a decoding process. Where the decoding process fails to converge, the decoder output is passed to the second detector for a subsequent detection and decoding process at a second time.

Abstract: In described embodiments, adaptive equalization of a signal in, for example, Serializer/De-serializer transceivers by a) monitoring a data eye in a data path with an eye detector for signal amplitude and/or transition; b) setting the equalizer response of at least one equalizer in the signal path while the signal is present for statistical calibration of the data eye; c) monitoring the data eye and setting the equalizer during periods in which received data is allowed to contain errors (such as link initiation and training periods) and periods in which receive data integrity is to be maintained (such as normal data communication).

Abstract: Various embodiments of the present invention provide systems, methods and circuits for power management and/or EMI reduction. As one example, a method for memory system access is disclosed that includes providing a first bank of memory; providing a second bank of memory; receiving a memory access request that includes assertion of a reference memory clock; accessing the first bank of memory using a first sub memory clock asserted relative to the reference memory clock; delaying a phase offset; and accessing the second bank of memory using a second sub memory clock asserted the phase offset after assertion of the first sub memory clock.

Abstract: A first SAS expander including at least phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander.

Abstract: In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.

Abstract: A flexible shunt for a vacuum circuit breaker can have a reduced straight length and improved flexibility even with an increased thickness within a predetermined accommodation space of a main circuit part. The flexible shunt comprises a pair of conductive plates, each including a clamp connecting portion configured as a flat conductive member, the clamp connecting portion being connected the clamp, a terminal side connecting portion configured as a flat conductive member, the terminal side connecting portion being connected to the terminal side, and a flexible curved portion configured to connect the clamp connecting portion to the terminal side connecting portion, the flexible curved portion being formed to be projected outwardly.

Abstract: Terminals for a vacuum circuit breaker include: a first terminal having a plurality of supporting rings, a plurality of finger contactors, and ring-shaped springs installed to contact an outer circumferential surface of the finger contactors so as to provide an elastic force to the finger contactors toward the center; a second terminal having an outer diameter larger than an inner diameter of the first terminal formed by an inner circumferential surface of the finger contactors of the first terminal, and configured by a bushing-type electric conductor; and an insulation guide member detachably fixed to a leading end of the second terminal such that an electric insulating property of the second terminal increases when the first and second terminals are disconnected from each other, having an electric insulating property, and tapered so as to have a decreased outer diameter as a distance from the second terminal becomes long.

Abstract: Disclosed is a spring actuator for a circuit breaker, the spring actuator comprises a spring configured to provide an elastic energy serving to perform a circuit opening operation or a circuit closing operation of a circuit breaker; a spring housing providing a space to compress or extend the spring; a movable supporting plate linearly movable in the spring housing; a linearly-movable shaft linearly-movable having a first position for charging an elastic energy by compressing the spring, and having a second position for releasing the spring; a driving mechanism configured to provide a rotatory power for linearly-moving the linearly-movable shaft; one rigid link configured to convert the rotatory power provided from the driving mechanism to a linear power and to transmit the linear power to the linearly-movable shaft; and a latch mechanism having a position for latching the spring such that the spring maintains a charged state.

Abstract: Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.

Abstract: A method for Dynamic Storage Tiering (DST) may include identifying a first storage tier with a performance characteristic. The method may include monitoring the utilization of the first storage tier to detect the placement of a hot spot. The method may include logically dividing a continuous range of a plurality of logical addresses into at least a first segment and a second segment so the first segment includes a proportionally larger amount of the hot spot. The method may include moving the first segment into a second storage tier or moving the second segment into the second storage tier. The method may include determining an amount of utilization of the first storage tier by hot spots. The method may include recommending a change in an amount of storage space in the first storage tier based upon the amount of utilization of the first storage tier by the hot spots.

Abstract: In one embodiment, an acoustic echo control (AEC) module receives an outgoing signal and an incoming signal, which, at various times, contains acoustic echo corresponding to the outgoing signal. The AEC module has a delay estimation block that estimates, in the time domain, the echo delay using an adaptive filtering technique. This delay estimation is used to align samples of the incoming signal having acoustic echo with the corresponding samples of the outgoing signal from which the acoustic echo originated. The AEC module determines whether or not samples of the incoming signal contain acoustic echo based on the aligned outgoing signal, and the determinations are applied to a hangover counter. The AEC module then suppresses acoustic echo in the incoming signal and adds comfort noise to the incoming signal. The amount of echo suppression performed is gradually increased or decreased based on comparisons of the counter to a hangover threshold.