Abstract: A layered test pattern for measuring registration and critical dimension (CD) for multi-layer semiconductor integrated circuits is disclosed. A first layer includes a first pattern having vertical and horizontal portions. A second layer is formed over the first layer and includes a second pattern having vertical and horizontal portions having nominal vertical and horizontal phase shifts with respect to the vertical and horizontal portions, respectively, of the first pattern. The vertical and horizontal portions include periodically repeating vertical lines and horizontal lines, respectively. The nominal phase shifts may be half of the period of the vertical and horizontal lines. A scatterometry tool measures the width of the lines and the phase shift of the first pattern relative to the second pattern. The width of the lines corresponds to CD, whereas the difference between the measured phase shift and the nominal phase shift indicates variation in registration.

Abstract: The present invention provides a method of packaging, storing, uploading, and executing a DOS based software module capable for being utilized as applications of a PCI device. The present invention may deliver both a binary image and a DOS executable of an application provided by the PCI device. The DOS executable may be utilized by a source level debugger for the development of the application of the PCI device as any changes to the CU can easily be viewed, debugged and corrected. As a result, testing changes become simple operation that does not require building a bundled binary image with the PCI option ROM. The present invention may provide a method for additional modules to be utilized during system startup time. Further, the present invention may provide an independent tool running under DOS without the presence of the PCI option ROM. Independent DOS executable module may be used to demonstrate the application for internal reviews.

Abstract: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

Abstract: The present invention is a method and system for translating method calls to version-specified method calls. An interface to an underlying object is provided. Applications communicating with the underlying object use the interface. The interface is separate from the underlying object. Version-specific underlying objects are generated. Each one of the version-specific underlying objects is a different version of the underlying object. A plurality of translation objects, one for each version-specific underlying object, are generated for communicating between the interface and each one of the version-specific underlying objects. A translation object is used for translating an interface method call invoked on the interface to a version-specific method call for the underlying object for each version of the underlying object. All translation objects are generated from a single proxy class and a single invocation handler class.

Abstract: A method of maintaining a count of active events of a process is provided by a start counter and a complete counter. The start counter maintains a first count of start events and may be operated upon only by the start event of the process. The complete counter maintains a second count of complete events and may be operated upon only by the complete event of the process. The count of active events is established by determining the difference between the first and second counts. The present invention further provides for re-setting the first and second counts of the start and complete counters, respectively, when one or both of the counters have reached a maximum count value.

Abstract: The present invention provides systems and methods for balancing a request load on device communication channels. A system includes a channel scanner, a processor, and a load balancer. The system may iteratively balance the request load on the communication channels. The device communication channels are typically connected between controllers and a system of devices. The channel scanner is configured for scanning the channels to determine the number or bandwidth of requests of each device. The processor may rank the devices by the number or bandwidth of requests of each device. The load balancer may allocate the requests between the channels based on the rank of the devices. For example, the load balancer may receive the rank order of the devices from the processor and allocate the requests based on the rank order. The load balancer may additionally allocate the requests based on present capabilities of the channels.

Abstract: A method of computing output delay in a mathematical model of an integrated circuit by sorting cells of original design of an the integrated circuit in a topological order. The original output delays for the sorted cells in the original design are computed in the topological order, to produce original output ramp times. The original output ramp times are propagated and original output delays are computed, and the original output ramp time and original output load for each cell is stored. The cells of the original design are modified to produce a modified design. For each modified cell in the topological order, a new output delay and a new output ramp time are computed and compared to the original output ramp time on the modified cell. When the new output ramp time substantially equals the original output ramp time for a modified cell, the calculations of the modified output ramp time for cells that are further down in the topological order are stopped.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data input signal in response to a first control signal and a second control signal. The second circuit may be configured to (i) generate the first control signal and the second control signal and (ii) determine whether the first circuit is coupled to (a) a first logic level circuit when in a first state and (b) an impedance circuit and a second logic level circuit when in a second state.

Abstract: While a semiconductor memory operates in a first operation mode with high security, an encrypted command is inputted and then decoded to acquire the first address information. After the semiconductor memory comes into a second operation mode where the level of security is lower than that of the first operation mode, a command is inputted. Then, the second address information is acquired from the command. A control circuit in the semiconductor memory generates an address of 10 bits by using the first address information as a high-order 4 bits and the second address information as a low-order 6 bits and outputs the address to a memory array. With this operation, it becomes possible to read/write data from/to the memory array.

Abstract: A method for designing and using a partially manufactured semiconductor product is disclosed. The partially manufactured semiconductor product, referred to as a slice, contains a fabric of configurable transistors and at least an area of embedded memory. The method contemplates that a range of processors, processing elements, processing circuits exists which might be manufactured as a hardmacs or configured from the transistor fabric of the slice. The method then evaluates all the memory requirements of all the processors in the range to create a memory superset to be embedded into the slice. The memory superset can then be mapped and routed to a particular memory for one of the processors within the range; ports can be mapped and routed to access the selected portions of the memory superset. If any memory is not used, then it and/or its adjoining transistor fabric can become a landing zone for other functions or registers or memories.

Abstract: A circuit comprising a plurality of first line buffers, an arbiter and a cache. The plurality of first line buffers may be configured to communicate on a plurality of first busses. The arbiter may be configured to perform an arbitration among the first line buffers. The cache block may be configured to (i) determine a particular policy of a plurality of policies in response to a first transaction request from one of the first line buffers winning the arbitration and (ii) generate a second transaction request based upon the first transaction request and the particular policy.

Abstract: The present invention is directed to a parallel processor language, a method for translating C++ programs into a parallel processor language, and a method for optimizing execution time of a parallel processor program. In an exemplary aspect of the present invention, a parallel processor program for defining a processor integrated circuit includes a plurality of processor commands with addresses. The plurality of processor commands may includes a starting processor command, and each of the plurality of processor commands includes one or more subcommands. When the processor integrated circuit executes the parallel processor program, the processor integrated circuit executes the staring processor command first and then executes the rest of the plurality of processor commands based on an order of the addresses.

Abstract: The invention is directed to a method and apparatus for supporting legacy mode fail-over drivers with an iSCSI network entity including multiple redundant controllers. In an exemplary aspect of the present invention, to support legacy mode fail-over drivers with an iSCSI network entity including multiple redundant controllers, the following configuration constraints may be placed on the iSCSI network entity and its iSCSI configuration: (1) the network device need have two or more redundant controllers; (2) the portals on each controller may or may not be formed into portal groups; (3) the portal groups may not span controllers (i.e., the target portal groups are limited in scope to a single controller); (4) the same iSCSI target name need be exported by all redundant controllers (i.e., the targets span all controllers of the iSCSI network entity, making the LUNs available to all controllers); (5) the target portal group numbers on the redundant controllers need have unique target portal group tags (i.e.

Abstract: Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit parameters associated with buffers identified in the table to identify whether a buffer identified in the table can be inserted to the respective internal vertex. If it can, an optimal insertable buffer is selected from the table and inserted to a selected internal vertex based at least in part on the comparison results. Also described is a computer process of creating the buffer type table.

Abstract: An apparatus comprising a plurality of first counters, a second counter, and a logic circuit. The plurality of first counters may each be configured to increment a first value in response to receiving one of a plurality of incoming data packets on an associated port. The second counter may be configured to increment a second value in response to a highest value of said first values being incremented. The logic circuit may be configured to generate an output representing a volume of packet traffic in response to the plurality of first values and the second value. The output signal generally indicates which of a plurality of ports is best suited for implementing flow control.

Abstract: A universal interface circuit and an associated method are provided that can supply a computer logic circuit, such as the components mounted upon an adapter card, with first and second inputs having first and second predetermined voltage levels, respectively, based upon power drawn from both first and second supply voltages. The interface circuit typically includes a first power supply circuit for providing the first input having the first predetermined voltage level in response to the first supply voltage. Additionally, the interface surface includes a regulator for generating an output having the second predetermined voltage level in response to the first supply voltage. The interface circuit further includes a second power supply circuit for providing an output that also has the second predetermined voltage level, albeit in response to the second supply voltage.

Abstract: A method and apparatus are provided for interfacing between a data source and a tightly-coupled memory. In the method and apparatus, a write data word and a write address are received from the data source and latched in a first clock cycle within a write buffer along a write data path, between the data source and the memory. The write data word is encoded according to an error detection code along the write data path. The write address and the write data word are applied to the memory from the write buffer. The write data word is accessible to the data source from the write data path or the memory beginning with a second clock cycle, which is a next subsequent clock cycle to the first clock cycle.

Abstract: A bank controller, an information processing device, an imaging device, and a control method are provided which enable improved data communication processing between FIFO memories of processing blocks and a synchronous DRAM. An arbiter determines the order of priorities in data communication performed between FIFO memories and associated banks. A precharge period detecting block detects the states of precharge of the banks. A register stores data required to determine the order of priorities (data indicating whether the banks are in a precharge period, data indicating whether data communication request signals are presented). This enables the arbiter to exclude FIFO memories that are associated with banks that are not allowed to perform data communication. Efficient data communication is thus implemented between the FIFO memories and the synchronous DRAM.

Abstract: A circuit generally comprising a first memory, a processor and a logic block is disclosed. The first memory may store (i) a write instruction to store a non-highest security value of at least three security values in a register and (ii) a jump instruction to a second memory. The processor may have a pipeline and may be configured to (i) bootstrap to the first memory while the register stores a highest security value of the security values and (ii) execute the jump instruction following the write instruction. The logic block may be configured to (i) detect the write instruction in an execution stage of the pipeline and (ii) store the non-highest security value in the register in response to detecting the write instruction in a write back stage of the pipeline.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA device directly attached to a SAS/SATA host controller. In an exemplary aspect of the present invention, it is determined whether a Serial ATA device is directly attached to a SAS/SATA host controller without using a SAS expander. When it is determined that the Serial ATA device is directly attached to the SAS/SATA host controller, an idle or active condition of a Serial ATA interface including the Serial ATA device and the SAS/SATA host controller is automatically detected. When the Serial ATA interface is in an idle condition, idle time of the Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state.