Patents Assigned to LSI
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Patent number: 7254761Abstract: A method for monitoring a fabrication of a circuit is disclosed. The method generally includes a step of (A) fabricating a chip only up to and including a first metal layer such that (i) a core region of the chip may has an array of cells, (ii) each of the cells may have a plurality of transistors and (iii) the chip may include a plurality of flip-flops. After the fabricating of step A has started, another step may be (B) designing a plurality of upper metal layers above the first metal layer. The upper metal layers (i) may interconnect a plurality of the cells to form the circuit, (ii) may form a plurality of scan chains from a number of the flip-flops not used in the circuit and (iii) may form a plurality of paths in the upper metal layers. Each of the paths generally connects a respective output of a first of the scan chains to a respective input of a second of the scan chains.Type: GrantFiled: November 28, 2005Date of Patent: August 7, 2007Assignee: LSI CorporationInventor: Gregory Crowell
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Patent number: 7253497Abstract: An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.Type: GrantFiled: July 2, 2003Date of Patent: August 7, 2007Assignee: LSI CorporationInventors: Hemanshu D. Bhatt, Jan Fure, Derryl D. J. Allman
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Patent number: 7254716Abstract: A circuit generally comprising a plurality of master modules and a supervisor module is disclosed. The supervisor module may be configured to (i) detect a target address and a particular master module of the master modules initiating a transaction on a bus, (ii) identify a predetermined authorization in response to the particular master module, the target address and a current security mode of at least three security modes and (iii) subvert the transaction in response to the predetermined authorization restricting the transaction.Type: GrantFiled: December 20, 2002Date of Patent: August 7, 2007Assignee: LSI CorporationInventors: Christopher M. Giles, Simon Bewick, Kalvin E. Williams
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Publication number: 20070177026Abstract: The least significant bits of respective count values of an H counter and a V counter are combined, to generate a timing signal defining a 2×2-size repeat block. A timing register including four registers each storing data which determines a color of each location within the repeat block is provided for each of input channels. A selector selects one of outputs of the timing registers based on the timing signal, and generates a signal designating a color of a pixel at a certain time for each of the input channels. A register storing black level correction data for each color is used in common by the input channels. For each of the input channels, an item of black level correction data at the certain time is selected based on the signal designating the color of the pixel at the certain time and input to a pre-processing circuit in each of the input channels.Type: ApplicationFiled: January 26, 2007Publication date: August 2, 2007Applicant: MegaChips LSI Solutions Inc.Inventor: Gen SASAKI
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Publication number: 20070180014Abstract: A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.Type: ApplicationFiled: March 22, 2007Publication date: August 2, 2007Applicant: LSI LOGIC CORPORATIONInventor: Mikhail Grinchuk
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Publication number: 20070179745Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.Type: ApplicationFiled: February 1, 2007Publication date: August 2, 2007Applicant: LSI LOGIC CORPORATIONInventor: Roger Yacobucci
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Publication number: 20070171916Abstract: For an electronic apparatus in which data is transferred between a plurality of processing devices and a memory, a technique is provided which prevents the data transfer from being restricted and allows the processing devices to operate efficiently. The order of priorities of data transfer operations through channels is changed on the basis of a relation between thresholds and the amounts of data remaining respectively in FIFO buffers. This prevents the FIFO buffers from becoming empty of data, or from being filled up with data, which allows the devices to operate efficiently.Type: ApplicationFiled: December 14, 2006Publication date: July 26, 2007Applicant: MegaChips LSI Solutions Inc.Inventor: Takashi MATSUTANI
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Publication number: 20070171737Abstract: The present invention provides a semiconductor storage device that requires no specialized circuit or the like for reading redundancy data from a redundancy region, and that is capable of freely changing the arrangement of the redundancy region in the memory array area. A semiconductor storage device of the present invention includes a memory array configured as shown below. The memory array includes a user region which is composed of given page units and where user data is stored, and a redundancy region which is composed of the same given page units and where redundancy data is stored. The area in the memory array can be used either as the user region or as the redundancy region.Type: ApplicationFiled: December 20, 2006Publication date: July 26, 2007Applicant: MegaChips LSI Solutions Inc.Inventors: Kumiko Mito, Takashi Oshikiri
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Publication number: 20070171710Abstract: A memory cell array includes a memory cell transistor storing data of a value in accordance with a set threshold voltage. A writing control unit controls writing of data in the memory cell transistor. A memory cell driving unit writes data in the memory cell transistor under the control of the writing control unit. The writing control unit is capable of setting at least three types of threshold voltages having different values for the memory cell transistor by controlling the memory cell driving unit, and uses only a plurality types of threshold voltages having values not adjacent to each other of the at least three types of threshold voltages in writing data in the memory cell transistor.Type: ApplicationFiled: December 21, 2006Publication date: July 26, 2007Applicant: MegaChips LSI Solutions Inc.Inventors: Kumiko MITO, Takashi Oshikiri
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Publication number: 20070171631Abstract: This invention is a lighting fixture to project even illumination onto flat panels. The fixture is a formed specular aluminum reflector with LEDs mounted to provide even and directed light, with modular connectors and power sources, allowing for variable lengths when combined with field adjustable housings and supports; or when mounted in a fixed length housing, to allow for linear lighting using any number of selectable lengths. This invention provides a pre-determined and directed light pattern requiring no field adjustment. The use of long life, weather resistant light emitting diodes provides for low maintenance and low energy consumption. The use of specular aluminum allows up to 95% of the light to be reflected to the surface, as well as provides heat sink properties further prolonging the life of the LEDs. By focusing all the available light on the desired area and eliminating stray light, lower wattage LEDs can be used.Type: ApplicationFiled: April 13, 2006Publication date: July 26, 2007Applicant: LSI Graphic Solutions plusInventor: Gerald Davis
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Patent number: 7248638Abstract: Provided are methods and apparatuses for use in wireless communication between a transmitter having plural transmit antennas and a receiver having plural receive antennas. A first data stream using a first transmit antenna weight vector and a second data stream using a second transmit antenna weight vector simultaneously are transmitted to the receiver. In addition, a first perturbation signal corresponding to the first transmit antenna weight vector and a second perturbation signal corresponding to the second transmit antenna weight vector are transmitted. Feedback regarding the first transmit antenna weight vector and the second transmit antenna weight vector is received from the receiver and is utilized to modify the first transmit antenna weight vector and the second transmit antenna weight vector.Type: GrantFiled: July 17, 2002Date of Patent: July 24, 2007Assignee: LSI LogicInventor: Brian C. Banister
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Publication number: 20070163993Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.Type: ApplicationFiled: April 2, 2007Publication date: July 19, 2007Applicant: LSI LOGIC CORPORATIONInventors: Wilbur Catabay, Wei-Jen Hsia, Hao Cui
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Publication number: 20070167868Abstract: A medical diagnostic instrument for the ergonomic effective and safe harvesting of specimen at targeted remote tissue sites includes a pistol grip style handle with a hand activated lever and a specialized elongated flexible double tube needle shaft inside of a protective sheath for use, in a preferred embodiment, within an endoscope. The length of needle shaft is adjusted using locking buttons. Moving another set of buttons sets the needle penetration depth. With a squeeze of the lever, a novel thin band drive mechanism advances the needle shaft out of its sheath, through adjacent tissue and into the targeted site. The double tube needle shaft incorporates a pointed distal tip attached to an innermost “grater” needle, which has sharp edged tissue cutting holes or “grating” features that are exposed by retracting back an overlying cover tube. Sliding back the cover tube is achieved via a cam. The sharp cutting surfaces of the grater tube communicate directly with a vacuum source attached near the handle.Type: ApplicationFiled: January 18, 2006Publication date: July 19, 2007Applicant: LSI Solutions, Inc.Inventor: Jude Sauer
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Patent number: 7246336Abstract: A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.Type: GrantFiled: December 3, 2004Date of Patent: July 17, 2007Assignee: LSI CorporationInventors: Andrej A. Zolotykh, Elyar E. Gasanov, Alexei V. Galatenko, Ilya V. Lyalin
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Patent number: 7245758Abstract: A method and system for collecting and analyzing photoemission data wherein illumination and photoemission images are acquired for a plurality of die, such as for each die on a wafer. Then, the images are overlaid, aligned, and assembled in a mosaic, thereby allowing analysis of the photoemission occurring across a plurality of die, such as across the entire wafer. Preferably, gathering this data allows statistical analysis of the photoemission such as analysis of commonly emitting locations to identify structures/cells that are sensitive to the manufacturing process.Type: GrantFiled: August 20, 2003Date of Patent: July 17, 2007Assignee: LSI CorporationInventors: Jeffrey Blackwood, Tracy Myers
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Patent number: 7246216Abstract: An apparatus comprising a first partition and a second partition. The first partition has a first file system comprising (i) a plurality of first clusters configured to store data having accesses faster than a first worst case data transfer rate and (ii) a dedicated space not used by the plurality of first clusters. The second partition has a second file system comprising a plurality of second clusters (i) configured to store data having accesses faster than a second worst case data transfer rate and (ii) occupying the dedicated space.Type: GrantFiled: July 14, 2004Date of Patent: July 17, 2007Assignee: LSI CorporationInventor: Paul R. Swan
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Patent number: 7246337Abstract: A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.Type: GrantFiled: December 8, 2004Date of Patent: July 17, 2007Assignee: LSI CorporationInventors: Alexander Andreev, Ivan Pavisic, Anatoli Bolotov
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Publication number: 20070162804Abstract: A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.Type: ApplicationFiled: March 7, 2007Publication date: July 12, 2007Applicant: LSI LOGIC CORPORATIONInventor: Robert Benware
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Patent number: 7242074Abstract: A method for reducing the parasitic capacitance in resistors, and a resistor design embodying this method are described. By creating a p-type or an n-type implant inside of an n-well or a p-substrate, respectively, where the n-well or p-substrate is located in a p-substrate or n-substrate, respectively, a capacitively coupled capacitor is formed in series connection with the parasitic inter-layer dielectric capacitance generated when the resistor is fabricated in the dielectric material. The depletion region formed thereby behaves as a series capacitor which reduces the overall capacitance of the assemblage. The n-well or p-substrate can be placed in electrical connection with a ground potential or brought to a chosen voltage to further increase the depletion region and reduce the capacitance of the resistor.Type: GrantFiled: December 6, 2004Date of Patent: July 10, 2007Assignee: LSI CorporationInventors: Sean C. Erickson, Jonathan Shaw, Kevin R. Nunn
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Patent number: 7243254Abstract: A memory controller is provided and a method for transferring data between the memory controller and a memory device. The memory controller can be implemented on an integrated circuit that also contains an execution unit. The execution unit can be clocked at a first clock rate, whereas the memory controller can be selectively clocked at either the first clock rate or a second clock rate that is approximately one-half frequency of the first clock rate. By clocking the memory controller at either the first clock rate or the second clock rate, the memory controller can accommodate different types of semiconductor memory. For example, the memory controller can control single data rate (SDR) DRAM memory if it is clocked at a first clock rate. Conversely, the memory controller can control double data rate (DDR) DRAM memory if it is clocked at approximately one-half the first clock rate.Type: GrantFiled: November 5, 2003Date of Patent: July 10, 2007Assignee: LSI CorporationInventors: Vijendra Kuroodi, Geeta Desai, Eric Hung