Abstract: A method and system for implementing a mirror addressing scheme in conjunction with a symmetrical data table are disclosed. The method includes receiving a first address. In response to determining that the first address corresponds to an upper portion of a data table, generating a second address from the first address, where the second address corresponds to a lower portion of the data table. The method further includes using the second memory address to access a memory array, whereby data corresponding to the upper portion of the data table is accessed from the lower portion of the data table. In one embodiment, determining that the first address corresponds to an upper portion of the data table is achieved by determining upper segment and lower segment boundaries for the first memory address determining that the most significant bit of the lower segment is asserted.

Abstract: An optimizing method for integrated circuits wherein coordinates are assigned to cells of a logic tree in a manner that maintains desirable cell density characteristics.

Abstract: When a specific pair of devices are selected or reselected for communications across a SCSI bus, a hardware state machine in each device restores the communication parameters that have been previously negotiated for this pair of devices. This prevents the devices from wasting bus time for the restoration.

Abstract: An interface is provided between a digital signal processor or the like and an output encoder or the like that is capable of counting a system clock of the digital signal processor, generally having a higher clock rate, with respect to at least one or more clocks generally having a lower clock rate. The digital signal processor system clock is passed to the interface that has at least one or more counters. When the accumulation of the system clock reaches a corresponding number of the other clocks, a domain module in the output encoder is triggered, and the corresponding clock counters are reset. The interface may be implemented as a software modeling routine suitable for utilization by a digital signal processor simulator to facilitate complete whole cycle simulation in which multiple clocks having various clock rates may be simulated and compared with a behavior reference. The interface provides cycle-by-cycle comparison of the clocks in an asynchronous domain.

Abstract: A method and apparatus for providing a ball grid array assembly formed from interlocking ball grid array packages is disclosed. Each of the ball grid array packages has interlocking edge features for mechanical connection, whereby joining the plurality of ball grid array packages via the interlocking edge features forms the interlocking ball grid array assembly. The interlocking ball grid array assembly may then be mounted on a PC board as a single unit.

Abstract: A method of motion compensation using temporal support of multiple fields of video to produce a progressive frame. The moving average of the motion compensated field lines temporally adjacent to the field to be de-interlaced are used, after a non-linear filtering, as the missing lines to complete the progressive video frame.

Abstract: A computerized system for analyzing information associated with a process unit. A database contains historical information relating to previously compiled information. A secure input receives criteria from a restricted source. A computer mathematically determines a limit based upon the criteria. An open input receives the information associated with the process unit from multiple test locations. A compiler selectively adds to the database of historical information the information. The computer also selects at least a portion of the information based upon selection criteria. In addition, the computer manipulates the selected information based upon manipulation criteria. The manipulated information is compared against the limit. An output indicates a first disposition of the process unit when the manipulated information violates the limit. The output indicates a second disposition of the process unit when the manipulated information does not violate the limit.

Abstract: A method for communicating on a SCSI bus permits out-of-band addressing and communication for normally non-addressable devices such as SCSI expanders and terminators. The method remaps 18 SCSI data lines for out-of-band operation and manipulates no more than those data lines. Some of the data lines are remapped for purposes of out-of-band signaling and data transfers. Advantageously, manipulation of only the SCSI data lines prevents the possible response of a device on the SCSI network that does not support the out-of-band operations. Accordingly, the disclosed method is backward compatible with existing SCSI networks while allowing implementation of devices having the increased functionality of out-of-band communication.

Abstract: A method and apparatus are provided for capturing data read from a memory device that is aligned with respect to a clock strobe signal originating from the memory device, which has constraints with respect to a local clock signal supplied to the memory device. The apparatus includes a circuit for capturing the data read from the memory device relative to the clock strobe signal to produce captured read data, a circuit for latching the captured read data relative to a sample clock signal, and a circuit for measuring a phase difference between the sample clock signal and the clock strobe signal and adjusting a phase of the sample clock signal as a function of the phase difference.

Abstract: A method for reducing the coupling capacitance between adjacent electrically conductive interconnect lines of an integrated circuit. An electrically conductive layer is deposited and etched to produce electrically conductive interconnect lines having negatively sloped sidewalls. An insulating layer is deposited on the electrically conductive interconnect lines using a directional deposition to create a void between and directly adjacent electrically conductive interconnect lines. The void has a substantially lower dielectric constant than the material of the insulating layer, which reduces the coupling capacitance between adjacent electrically conductive interconnect lines.

Abstract: An improved multimedia encoder having features advantageous for use in a computer system. These features provide for the reduction of bandwidth and storage requirements, the enhancement of noise immunity, the evening of computational loading, and the use of multimedia drives for general purpose data storage. In one embodiment, the encoder receives image data representing a sequence of video frames and display text data representing a sequence of text fields to be overlaid on the sequence of video frames. The multimedia encoder produces a compressed video frame only for each subsequent video frame which is different from the current video frame. After each video frame is compressed, it becomes the current frame. The multimedia encoder provides error correction encoding to enhance noise immunity, and performs interframe compression using a dynamic search area to even out computational loading.

Abstract: An aluminum layer formed over an integrated circuit structure is patterned to form a plurality of aluminum metal lines. The patterned aluminum metal lines are then anodized in an acid anodizing bath to form anodized aluminum oxide on the exposed sidewall surfaces of the patterned aluminum. The anodization may be carried out until the anodized aluminum films on horizontally adjacent aluminum metal lines contact one another, or may be stopped prior to this point, leaving a gap between the anodized aluminum oxide films on adjacent aluminum metal lines. This gap may then be either filled with other low k dielectric material or by standard (non-low k) dielectric material. A capping layer of non-porous dielectric material is then formed over the porous anodized aluminum oxide.

Abstract: A method for etching a surface of an integrated circuit. A layer of photoresist is applied to the surface of the integrated circuit. The layer of photoresist is exposed and developed, and the surface of the integrated circuit is etched with an etchant that contains chlorine. The surface of the integrated circuit is exposed to tetra methyl ammonium hydroxide to neutralize the chlorine, and rinsed with water.

Abstract: A method of control cell placement for an integrated circuit design includes the steps of receiving as input a datapath description including an initial set of coordinates for a plurality of control cells; ordering the plurality of control cells in a sequence (1, 2, 3, . . . , n) according to distance between each of the plurality of control cells and at least one fixed control cell in the plurality of control cells wherein n is the number of control cells in the datapath description; iteratively calculating globally optimum coordinates for the each of the plurality of control cells according to the sequence i=1, 2, 3, . . . , n from a global maximum of a control cell placement function; and generating as output the calculated globally optimum coordinates for the each of the plurality of control cells.

Abstract: A method for making a gate in an integrated circuit. A gate layer is formed on a substrate, and a blocking layer is formed on the gate layer. The blocking layer is masked with a photoresist layer, and the photoresist layer is developed to define an exposed gate area. The blocking layer is etched in the gate area to expose the gate layer in the gate area, and the photoresist layer is removed. A metal layer is formed on the blocking layer and on the gate layer in the gate area. The metal layer is selectively reacted with the gate layer in the gate area to form a hard mask over the gate layer in the gate area. The metal layer is removed from the blocking layer. The blocking layer is selectively etched without substantially etching the hard mask in the gate area, to expose the gate layer surrounding the gate area. The exposed gate layer is etched to define a gate in the gate area. The hard mask remains on the gate, and functions as an electrical contact to the gate.

Abstract: The specification discloses a for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves. The steps of the method include inserting a plurality of auxiliary nodes into the, defining discrete, approximate scales for delay, load, and ramp time, constructing a set of buffers chains for later insertion into the net tree, determining for each node on the tree a tradeoff function relating ramp time, departure time and load at the node, for each node, removing combinations of the tradeoff functions and the buffer chains, which when inserted into the tradeoff function, lead to a ramp time which exceeds a predetermined maximum allowable ramp time, for each node, using the tradeoff function to determine a minimum delay to insert, and inserting the buffer chain corresponding to the minimum delay as determined by the tradeoff function.

Abstract: A memory array has memory elements arranged in rows and columns. Each column has a respective bit line. A plurality of bit line input-output nodes are each switchably coupled to either a respective one of the bit lines or another one of the bit lines.

Abstract: A capacitor has a titanium nitride layer deposited on a silicon substrate for stress reduction and adherence promotion, and a layer of tantalum is deposited thereon. The tantalum layer is oxidized to produce a tantalum pentoxide layer. A top electrode of metal or polysilicon is then deposited on the tantalum pentoxide layer. The top electrode may be made from polysilicon or a similar semiconducting material so that a space charge layer will form in the electrode which will change the rate at which the capacitor charges and discharges. Alternatively, the top electrode may be made from metal to provide an optimal linear response for use in analog applications. Further, an undoped polysilicon layer may be provided above the tantalum pentoxide layer to store charge for non-volatile memory applications. For this purpose, polysilicon can be used to form the top electrode; alternatively, materials such as silicon nitride may be used.

Abstract: This invention provides a circuit and a method for providing an override voltage to control gates through boosting of a selected word line for TWIN metal oxide, nitride semiconductor MONOS memory. The boosted voltages are required to program, erase and read the 2-bit MONOS memory cell in this invention. This invention relates to providing a means of using capacitive coupling between selected word lines and neighboring control gates to boost the voltage for the program, erase and write modes of MONOS memory. Capacitive coupling to boost the voltage on the control gates adjacent to the selected word lines is used instead of generating the required boosted voltage through the control gate and bit line decoders and drivers. This voltage boosting method saves address decoder silicon area, decoder circuit complexity, reduces address decode set-up time, and eliminates the need for extra voltage supplies for address decoders.

Abstract: Channels are routed in an integrated circuit layout by reserving grid positions for buffers. Cell pins are identified at different y-coordinates to be connected by the channel. A determination is made as to the necessity of a jog between vertical segments, and if so, a y-coordinate is assigned to each such jog. An x-coordinate is assigned to each channel segment extending across the y-coordinates. Y-coordinates are assigned to buffers to be connected to the channel.