Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first signal and a second signal in response to (i) a select signal, (ii) a first difference signal and (iii) a second difference signal. The second circuit may be configured to present a modulated output signal in response to the first signal, the second signal and a control signal. The first circuit may alternately operate on one of either (i) the first difference signal or (ii) the second difference signal. In one example, the present invention may be implemented as a SECAM video encoder.

Abstract: A minimum core size of an integrated circuit chip is estimated for given parameters of an existing technology. The average wire length for the nets is calculated, and the centers of each cell are assigned to x,y coordinates to minimize wire length. The widths of routing channels between consecutive columns, and their associated core sizes are estimated based on the cell placement and the existing technology parameters. The minimum core size is identified from the estimated core sizes.

Abstract: A mold for use in encapsulating an integrated circuit, wherein an encapsulant is injected into the mold during packaging of the integrated circuit. The improvement to the mold is a shaped member having an abutting surface for contacting a surface of the integrated circuit and thereby substantially preventing encapsulant from adhering to the surface of the integrated circuit, whereby the surface of the integrated circuit is left exposed. Because the surface of the integrated circuit is left exposed, the encapsulant used to encapsulate the integrated circuit does not form a thermal barrier between the integrated circuit and the exterior of the package. Thus, the packaged integrated circuit is able to more efficiently conduct heat away from the integrated circuit.

Abstract: A method of processing a semiconductor wafer and an associated semiconductor wafer arrangement which inhibits “punch through” and increases the yield of functional semiconductor wafers during the fabrication thereof is disclosed. A method of forming a semiconductor with a substrate and a feature on the surface of the substrate is disclosed: Forming a spacer layer that contacts the feature. A barrier layer of silicon nitride can be deposited on the surface. Contacting the barrier layer with the spacer layer, prior to removing the barrier layer. Align a contact void with the barrier layer and spacer layer. Align a contact void such that the etch properties of the barrier layer prevents “punch through”.

Abstract: A multiplication accumulation circuit (abbreviated as “MAC”) has five input buses that carry signals for operands A, B, C, D and E, a control bus that carries signals for controlling the operations performed on the received operands, and an output bus that carries a signal generated by the MAC. Each of operands A, B, C and D can be four different operands that are used as follows by the MAC: (1) to perform two multiplications simultaneously, and (2) to perform an addition of the products of the two multiplications and the fifth operand E, e.g. generate on the output bus a signal of value A*C+B*D+E. Alternatively, operands A and B can be, respectively, the upper and lower halves of a first double word to be used as a multiplicand. Similarly, operands C and D can be the upper and lower halves of a second double word to be used as a multiplier.

Abstract: A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.

Abstract: An integrated circuit package manufacturing process is described which reduces or eliminates the formation of voids in a molding compound between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. Electrically conductive vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the vias and the air space.

Abstract: In the present invention a bit line decoder scheme is described that connects data and voltage to a plurality of bit lines of a dual bit flash memory array. The bit lines are connected to a plurality of intermediate data lines by a first decoder unit and the intermediate data lines are connected to a plurality of data lines of the sense amplifiers by a second decoder unit. In one embodiment the voltage is connected to a selected bit line through a separate decoder unit and in a second embodiment the voltage is connected through the decoder unit connected to the intermediate data lines.

Abstract: A method of fabricating a semiconductor device including the following steps of: forming a first insulating layer, a first conductive layer and a stopper layer over a semiconductor layer; forming a mask insulating layer on the first conductive layer in a logic circuit region; forming a conductive layer in a formation region of word gate layers and common contact sections and forming gate electrodes; anisotropically etching the second conductive layer to form control gates in the shape of sidewalls and a conductive layer of the common contact sections, in a memory region; and patterning the third conductive layer and the first conductive layer to form word gates and word lines.

Abstract: The present invention discloses a novel method and system for accessing a semiconductor device at multiple operating speeds. The novel method and system of the present invention allows access to a semiconductor device by a pipeline circuit in which modification of the pipeline circuitry is not required to achieve multiple operating speeds. An example of the invention may be the utilization of an internal clock to control internal pipeline which may allow adjustment of an effective operating speed of a semiconductor device.

Abstract: In a voltage controlled oscillator (VCO) having a voltage-current conversion circuit, a ring oscillator, and a main power supply for feeding a power supply voltage to these components, it is constructed so that a voltage which is fed to the voltage-current conversion circuit and ring oscillator may be applied with an internal voltage via a regulator circuit, thus effecting an oscillation output having only slight variations to the variations of the power supply voltage. Therefore, a phase synchronous circuit such as PLL circuits may be maintained at a locked status. In some instances, such a VCO may be modified not only to stabilize the dynamic range to the VCO control voltage, but also to switch the dynamic range. Thus, the oscillation frequency oscillated and outputted by the ring oscillator may be stabilized even upon the occurrences of the variations of the power supply voltage Vcc which is fed at a locked status.

Abstract: An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber.

Abstract: The present invention involves a method for reducing delay of a net. The method includes constructing a time-space grid, said time-space grid corresponding to a net, passing a wave through the time-space grid, said wave having a wave value, and inserting a buffer at a point on said time-space grid where insertion of the buffer increases a wave value. The buffer can be a negative buffer or positive buffer. Generally, a second wave is passed through the time-space grid simultaneously with the first wave. Typically, the second wave and the first wave are inverted.

Abstract: A method for creating a die that has some bond pads that are compatible with wire bonding and others that are compatible with solder bonding. A layer of copper is disposed over aluminum bond pads and selectively removed from those bond pads that are desired to be compatible with wire bonding.

Abstract: A system for indicating an amount of a process liquid contained within an interior of an ampoule. A first conduit is in selective fluid communication with the interior of the ampoule, and has a first opening configured for disposal below an upper surface of the process liquid. The first conduit introduces a carrier gas into the interior of the ampoule. A second conduit is also in selective fluid communication with the interior of the ampoule, and has a second opening configured for disposal above the upper surface of the process liquid. The second conduit receives the carrier gas from the interior of the ampoule. A pressure differential sensor is disposed between and is in selective fluid communication with the first conduit and the second conduit. The pressure differential sensor senses a pressure differential between the first conduit and the second conduit.

Abstract: A source pulsed complementary metal oxide semiconductor static random access memory offers higher cell stability, lower bit line delay, and lower standby power than previously available in low-voltage devices. A memory cell includes a first pull-up device, a first pull-down device connected to the first pull-up device, a first cell access device connected to the first pull-down device, a second pull-up device connected to the first pull-up device, a second pull-down device connected to the second pull-up device, and a second cell access device connected to the second pull-down device wherein the first cell access device and the second cell access device each have a gate connected to a word line that is driven to a voltage less than Vss except during cell access and is pulsed to Vdd during cell access.

Abstract: A set-associative cache having a selectively configurable split/unified mode. The cache may comprise a memory and control logic. The memory may be configured for storing data buffered by the cache. The control logic may be configured for controlling the writing and reading of data to and from the memory. The control logic may organise the memory as a plurality of storage sets, each set being mapped to a respective plurality of external addresses such that data from any of said respective external addresses maps to that set. The control logic may comprise allocation logic for associating a plurality of ways uniquely with each set, the plurality of ways representing respective plural locations for storing data mapped to that set. In the unified mode, the control logic may assign a first plurality of ways to each set to define a single cache region.

Abstract: Techniques are described for fabricating a pair of &bgr;-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. In particular, the lengths of respective channel regions for the transistors are substantially the same, and portions of each gate electrode extending above a channel region include only dopants of a single conductivity type. The techniques can be incorporated into a standard CMOS process.

Abstract: In the present invention a twin MONOS metal bit line array is read and programmed using a three dimensional programming method with X, Y and Z dimensions. The word line address is the X address. The control gate line address is a function of the X and Z addresses, and the bit line address is a function of the Y and Z addresses. Because the bit lines and the control gate lines of the memory array are orthogonal a single cell can be erased with an adjacent memory, having the same selected bit and control gate lines, being inhibited from erase by application of the proper voltages to unselected word, control gate and bit lines.

Abstract: In accordance with the invention a high-k gate dielectric is formed by the steps of first forming a silicon oxide layer over a silicon substrate and then exposing the silicon oxide to a flux of low energy plasma containing metal ions which, when inserted into silicon oxide, form a high-k dielectric material suitable for use as a high-k gate dielectric. In one embodiment, the silicon oxide is exposed to a first plasma containing a first species of metal ions and then to a plasma of another species of metal ions which, when inserted into the silicon oxide with the metal ions in the first plasma, further increase the dielectric constant of the silicon oxide.