Abstract: A method for fabricating a microstrip package to optimize signal trace impedance control is disclosed. The method includes patterning a plurality of signal traces on a multilayer substrate, and patterning a plurality of guard traces on the multilayer substrate, that are interspersed alternately among the signal traces to provide noise shielding between the signal traces. In a further embodiment, the traces are patterned on the substrate with a width that is adjusted at different locations based on the presence the guard traces to enable the package to meet a particular impedance requirement.

Abstract: A method of testing an integrated circuit. The thermal energy of the integrated circuit to adjusted to a first temperature, and a first set of electrical characteristics of the integrated circuit are sensed at the first temperature. The first set of electrical characteristics are recorded in association with an identifier for the integrated circuit. The thermal energy of the integrated circuit is adjusted to a second temperature, and a second set of electrical characteristics of the integrated circuit are sensed at the second temperature. The electrical characteristics of the second set correspond to the electrical characteristics of the first set. The second set of electrical characteristics are also recorded in association with the identifier for the integrated circuit.

Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished.

Abstract: A method of estimating the number of available transit connections, or porosity, of a hardmac for a logic design routing tool includes the steps of calculating a total metal layer capacity of a hardmac, calculating an absolute porosity of the hardmac from the total metal layer capacity and an internal connection density, and calculating a relative porosity of the hardmac from the total metal layer capacity and the absolute porosity.

Abstract: A method for characterizing cell interconnect delay is disclosed that may be included in a library for use with logic design tools. A method of characterizing cell interconnect delay includes the steps of (a) receiving as inputs a plurality of input ramptimes and a plurality of interconnect lengths for a selected cell, and (b) calculating an output ramptime and a total cell delay including a cell delay and an interconnect delay for each of the plurality of input ramptimes for each of the plurality of interconnect lengths for the selected cell from the inputs.

Abstract: A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer.

Abstract: A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.

Abstract: The present invention involves a method for determining constant pins in a combinational circuit. The method comprises the steps of associating an input of a combinational circuit with a first variable and a second variable, wherein said second variable is the compliment of said first variable, computing for a first logical cell interconnected to said input a first canonical representation, wherein said first canonical representation is a function of the operation of said first logical cell and a function of said first value, computing for said first logical cell a second canonical representation, wherein said second canonical representation is a function of the operation of said first logical cell and a function of said second value, determining whether one of said first and second canonical representations is equal to zero.

Abstract: A self-timing memory circuit with supply degradation compensation comprising a first self-timing circuit and a second self-timing circuit. The first self-timing circuit may be configured to generate a first signal that may be minimally affected by power supply degradation and/or variation. The second self-timing circuit may be configured to generate a second signal, where an effect of the power supply degradation and/or variation on the second signal is maximized.

Abstract: A system for interconnecting a plurality of interdependent fiber channel loops or fabrics. The system preferably comprises a first server which includes a PCI bus and a fibre channel to PCI bus adapter for each one of the plurality of the independent fibre channels. Each fibre channel to PCI bus adapter is configured to connect one of the plurality fibre channels to the PCI bus at the first server. The plurality of independent fibre channels then communicate with each other across the PCI bus of the first server utilizing the intelligent I/O (I2O) routing of the fibre channel to PCI bus adapters. The plurality of fibre channels are configured to communicate with the other fibre channels, as well as the first server via the PCI bus. This system can be configured such that any one of the plurality of fibre channels can include one or more devices connected thereto in addition to the first server.

Abstract: A Register Transfer Language (RTL) annotation software tool that: (1) automatically calculates new RTL of a circuit to facilitate subsequent RTL level Engineering Change Orders (ECOs) on a circuit where gate level changes have occurred during layout; and (2) automatically calculates a gate level netlist that corresponds to the RTL ECO which can be fed to modern layout tools with minimal disruption to the existing layout. In a preferred embodiment, the tool is software driven, iterative, and tracks any changes that need to be made for any given circuit described by a hardware description language (HDL) though a series of intermediate and preliminary data files. The software receives input in the way of user input, constraints, and an RTL description for a pre-ECO circuit, and outputs the post-layout annotated RTL description.

Abstract: A method of fabricating an integrated circuit using photolithography and an antireflective coating. An antireflective coating is formed on a substrate wherein the antireflective coating is electrically polarizable. A photoresist coating is formed on the antireflective coating on a side opposite from the substrate and the photoresist is exposed to activating radiation. The antireflective coating is subjected to an applied electric field at substantially the same time as the photoresist is exposed to activating radiation. The radiation absorption coefficient of said antireflective coating is increased and the refractive index of said antireflective coating is changed to be substantially equal to the refractive index of said photoresist coating.

Abstract: This invention comprises an improved method of planarizing, an integrated circuit formed onto a semiconductor substrate and the planarized semiconductor substrate. Improved planarity is accomplished through the use a first and second stop layer separated by a filler layer. A first stop layer is used to define active and trench regions. A filler layer is then applied over the surface of the substrate and a second stop layer is applied on top of the filler layer. The second stop layer is patterned through etching. The pattern etched into the second stop layer is used to control chemical mechanical polishing that planarizes the surface. Patterns can be a reverse image of an active mask or a continuous pattern. In addition CMP can be used to create a condition of equilibrium planarity before the second stop layer is applied. The stop layers can comprise polysilicon, silicon nitride, or another material that is harder than a dielectric oxide material used as filler material.

Abstract: A process for forming an integrated circuit structure characterized by formation of an improved barrier layer for protection against migration of copper from a copper-containing layer into low k dielectric material while mitigating undesired increase in dielectric constant and mitigating undesirable interference by materials in the barrier layer with subsequent photolithography.

Abstract: A source pulsed, dynamic threshold complementary metal oxide semiconductor static random access memory dynamically controls cell transistor threshold voltage to increase cell stability, decrease cell standby power, and reduce cell delay. A memory cell includes a low storage node and a high storage node wherein the low storage node is driven below Vss during a read access and the high storage node is driven above Vdd during the read access.

Abstract: An improvement in the formation of low dielectric constant carbon-containing silicon oxide dielectric material by reacting a carbon-substituted silane with an oxidizing agent is described, wherein the process is carried out in the presence of a reaction retardant. The reaction retardant reduces the sensitivity of the reaction to changes in pressure, temperature, and flow rates, and reduces the problem of pressure spiking, resulting in the formation of a deposited film of more uniform thickness across the substrate as well as a film with a smooth surface, and a reduction of the amount of carbon lost during the reaction.

Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.

Abstract: A method of generating a trace library includes the steps of receiving as inputs a plurality of technology dependent parameters and a trace template and generating a trace layout from the inputs.

Abstract: A low threshold voltage MOS device on a semiconductor substrate is disclosed. The substrate has an upper surface, and a first well region is disposed in said semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The first well region includes a dopant of a first conductivity type having a first average dopant concentration. Source and drain regions of a second conductivity type are laterally spaced from each other and are disposed in the first well region, the source and drain regions extending downwardly from the semiconductor substrate upper surface a predetermined distance. A channel region comprising the first well region of the first conductivity type is disposed between the source and drain regions. The channel region also extends at least the predetermined distance below the semiconductor substrate upper surface.

Abstract: A method and system for creating logical units (LUNs) in a RAID system by allocating proportional amounts of disk storage space to each LUN. Proportional allocation of disk space for different LUNs allows for the selective mapping of more data from the LUN to be mapped to some of the different disks to better optimize the I/O performance in a RAID system. The LUN is divided into a plurality segments or strips are allocated to predetermined disks in a predetermined proportional manner. A proportional create statement defines the proportional mapping and an intelligent RAID controller manages the proportional mapping of information.