Abstract: A double data rate (DDR) circuit for testing of a high speed DDR interface using single clock edge triggered tester data. The DDR testing circuit includes a first register, a second register, and a multiplexer (MUX). A clock signal is fed to the first register and the MUX. The inverse of the clock signal is fed to the second register. A tester data signal is fed to the first register which generates a latched tester data signal which is fed to the MUX. The inverse of the latched tester data signal is fed to the second register which generates a transformed tester data signal which is fed to the MUX. The MUX generates a combination of the latched tester data signal and the transformed tester data signal for transmission as an applied test data signal. The resulting applied test data signal has double the data rate of the tester data signal upon which it is based.

Abstract: A luminaire assembly includes a ballast housing, a wiring box mounted on an upper end of the ballast housing, and an optical assembly mounted on a lower end of the ballast housing. The ballast housing preferably includes a pair of identically configured ballast housing members that are integrally formed from sheet metal and folded by hand prior to final assembly of the ballast housing. The wiring box includes bent tabs that pivotally support the ballast housing between operative and inoperative positions to simplify installation of the luminaire assembly at a site. A hook and rotatable connector are provided to support the wiring box from a luminaire support member. An optional spacer box is provided to space the ballast housing from the wiring box as may be required in certain high wattage applications. The optical assembly is supported below the ballast housing by a pair of support arms that depend from the ballast housing and releasably engage with the optical assembly.

Abstract: A sign frame assembly for supporting a flexible fascia. In one embodiment, a frame member extends in a first direction and has first and second bracket-mounting sections spaced apart from each other in the first direction. First and second brackets have inner and outer opposite ends. The inner end of the first bracket is attached to the first bracket-mounting section of the first frame member. The inner end of the second bracket are pivotally mounted to the second bracket-mounting section of the frame member. First and second elongated fascia attachment members are affixed respectively to the outer ends of the first and second brackets. A flexible fascia having oppositely disposed edges is connected to the first and second elongated members.

Abstract: An apparatus for detecting a predetermined pattern of bits in a data bitstream includes a series of detecting elements (2-6), each detecting element in the series corresponding to a predetermined bit in the predetermined pattern. Each detecting element receives a data bit from the data bitstream (8), the corresponding predetermined bit in the predetermined pattern and an error signal from a previous detecting element in the series. The output of each detecting element is an error signal indicative of the number of mismatches between the data bit and the corresponding predetermined bit in the predetermined pattern, both in previous detecting elements in the series in previous clock cycles and in the current detecting element in the current clock cycle. The error signal of the final detecting element (6) of the series is coupled to a logic control element (18) for detecting that a maximum allowed level of mismatches has been detected.

Abstract: A current-mode peak detector circuit is disclosed. The current-mode peak detector circuit includes an input transistor for receiving an input current that impresses a voltage on a control node, a pair of transistors for providing an output current in response to the voltage at the control node, and a decay control circuit for controlling the decay of the voltage at the control node such that the output current is representative of a peak value of the input current signal. A clamp circuit may be provided for clamping the input voltage to a predetermined level. All of the elements of the current-mode peak detector circuit may be realized using transistors for facilitating integration of the current-mode peak detector circuit on an integrated circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure.

Abstract: A transmission system for transmitting a signal from a host to a transmission medium is disclosed. The transmission system includes a current-mode digital-analog converter, an on-chip low-pass filter, a line driver, and output impedance control. Further, a method for transmitting a signal from a host to a transmission medium using on-chip filtering is disclosed. More specifically, an apparatus and method for providing precise control of the filter cut-off frequency at high frequencies is disclosed. The transmission system and method can be used in transmission of Ethernet signals onto an unshielded twisted pair cable. In addition, with appropriate modification, the transmission system and method can be used for transmitting ATM or other signals onto a transmission medium.

Abstract: An architecture for a low power, high density (smaller area) asynchronous memory comprises memory cells including a forward inverter and a feedback inverter disposed in a back-to-back arrangement (i.e., back-to-back inverters), two write access transistors, a read inverter, and a read access transistor. The architecture employs a double ended write into the memory cells wherein Write Bit Lines coupled to write access transistors are precharged to Vdd−Vtn, or, alternately Vdd, when the signal Write Enable (WE) is low (i.e., “0”).

Abstract: A method of altering topology of a serial bus having a plurality of nodes interconnected in a tree topology in order to increase data rates between the plurality of nodes includes the step of obtaining a current topology representation of the serial bus which indicates a first node of the plurality of nodes is coupled to a second node of the plurality of nodes via a third node of the plurality of nodes. Another step of the method includes obtaining data rate capabilities of each node of the serial bus. The method further includes determining based upon the current topology representation of the serial bus and the data rate capabilities of each node that the third node of supports a third maximum data rate that is slower than a first maximum data rate supported by the first node and a second maximum data rate supported by the second node.

Abstract: A water leakage detecting apparatus is capable of detecting water leakage of a water pipe precisely and at low cost. The water leakage monitoring apparatus includes vibration/electric converter for converting an acoustic vibration transmitted to a water pipe into an electrical signal. A signal discriminator processes an output signal of the vibration/electric converter to detect a signal of a predetermined band being held below a predetermined level continuously beyond a continuing condition to generate a sound interruption detection signal. A counter counts the number of occurrences of the sound interruption detection signal.

Abstract: A method for wafer bumping includes the steps of spreading a layer of an electrically conductive paste on a surface having a plurality of electrical contacts and exposing a beam-paste interaction volume to a beam of energy to bond a portion of the layer of the electrically conductive paste to at least one of the plurality of electrical contacts for forming a wafer bump.

Abstract: A video decoder is provided with robust error handling and concealment. In one embodiment, the video decoder detects syntactic, semantic, and coding errors in encoded slices of macroblocks. An error handler determines the number of remaining un-decoded macroblocks in the corrupted slice and replaces these corrupted macroblocks using substitute DCT coefficient matrices and motion vectors. The zero-frequency DCT coefficient of each substitute matrix is set equal to the zero-frequency DCT coefficient of the last uncorrupted macroblock, while the higher frequency DCT coefficients are set equal to zero. The substitute motion vectors are provided from a concealment vector memory which buffers the motion vectors of the previous macroblock row. In this way, intelligent approximations are made for the missing macroblocks, effectively masking the video bitstream error.

Abstract: In the prior arts a twin MONOS memory erase is achieved by applying a positive bias to the bit diffusion and a negative bias to the control gate. The other word gate and substrate terminals are grounded. But the voltage of word gate channel adjacent to the control gate can dramatically influence erase characteristics and speed, due to the short control gate channel length, which is a few times of the carrier escape length. A negative voltage application onto the word gate enhances erase speed, whereas a positive channel potential under the word gate reduces erase speed. By effective biasing of the memory array, word line or even single memory cell level erase is possible without area penalty, as compared to erase blocking by triple well or physical block separations of prior art. Near F-N channel erase without substrate bias application and program disturb protection by word line voltage are also included.

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: Information about an article to be carried is written into a non-contact type IC card by a reader/writer on the side of a sending trade, and the IC card into which the information has been written is accommodated in a carrying bag to which a tag is provided and a paper-made slip is attached, and the carrying bag is stuck to the article to be carried. A conveying trade collects the article to which the carrying bag is stuck so as to convey it to a desired receiving trade. The information written into the IC card carried together with the received article is read by the reader/writer on the side of the receiving trade.

Abstract: An integrated circuit device including a semiconductor die and optical signal emitting diodes for communicating different color optical signals, such as multi-phase clock or trigger signals, to individual circuits on the die. Each circuit includes a filter to discriminate the desired frequency and a photosensitive active device implemented on the die for converting the received optical signal to an electronic signal for clocking or triggering a local circuit (e.g., a data storage register). Translucent material encapsulates the emitter diode and the die. The optically communicated signal has very low skew, which is independent of the topology of the die.

Abstract: A method and apparatus dissipates heat generated by an electronic device. The apparatus includes a channel structure that is in thermal communication with heat generated by the electronic device. The apparatus further includes a pump array operative to advance fluid within the channel structure. In addition, the apparatus includes a baffle array positionable in relation to the channel structure in a first group position and a second group position, wherein fluid advancing within the channel structure is diverted to flow (i) in a first flow path defined in the channel structure when the baffle array is positioned in the first group position, and (ii) in a second flow path defined in the channel structure when the baffle array is positioned in the second group position.

Abstract: A character display device includes a memory for storing on-screen display (OSD) character data and wallpaper (background) character data, and shift registers for outputting the corresponding one of those character data stored in the memory in accordance with a command to display one of the OSD character data and of the wallpaper character data. The character display device combines the OSD character data and the wallpaper character data using of a mixer, when the timing for displaying the OSD character data and that for displaying the wallpaper character data coincide with each other, so that both character data can be displayed in a superimposed manner.

Abstract: A method of conditional branching in a pipelined processor. The method comprising the steps of (A) prefetching a branch target address in response to encountering a branch instruction, in prediction of taking a branch, and (B) evaluating between (i) taking the branch and (ii) not taking the branch substantially contemporaneously with prefetching the branch target address.

Abstract: An apparatus (22) for reducing noise in a tracking error signal receives input signals from an array (5) of photodetectors, each input signal indicating the amount of laser light incident on the corresponding photodetector reflected from an optical disc. The input signals from diagonal pairs of photodetectors are summed and then filtered and digitized to produce a pair of digital input signals. A signal difference generator (20) produces first and second difference signals when either the first or the second digital input signals are received. The first and second difference signals are received by a programmable timing element having a user programmable device (41) and a signal limiting device (32, 33, 34, 35) for limiting the duration of the first or second difference signals provided at respective first or second outputs of the programmable timing element to a user programmable maximum value.

Abstract: A distributed computer aided design (CAD) system includes a CAD server station and one or more CAD client stations remote from the server station but connectable thereto via a communications medium such as an intranet or the internet. The CAD server station includes a CAD tool for performing CAD tasks and a communications interface. The CAD client stations include display and data entry facilities for displaying a design parameter entry document to a user and for accepting design parameters entered by the user, as well as a communications interface for transmitting entered design parameters via the communications medium to the server station. The CAD tool at the server station is configured to receive the design parameters from the client station, to perform CAD tasks based on the design parameters and to return processed design data to the server station via the communications medium. The client station can include a workstation with a web browser capability.