Abstract: A semiconductor package is disclosed. According to one embodiment, the package comprises a substrate having a top surface with traces thereon and a bottom surface with solder balls thereon, the substrate comprising at least three material layers defining at least four substantially planar metal layers, wherein one of the metal layers comprises a reference layer that serves as a reference to both traces on a metal layer above the reference layer and traces on a metal layer below the reference layer. A semiconductor die is mounted to the substrate and bonding wires electrically connect the semiconductor die to the traces on the top surface of the substrate. The traces on the top surface of the substrate are electrically connect to the solder balls through vias and possibly through routing on another metal layer.

Abstract: The present invention is a method for cleaning the cavities in electronic components by providing a semiconductor component having an outside surface and a cavity therein. The component including hole in the outside surface enabling fluid flow in to or out of the cavity. The component is immersed in a solvent bath where solvent is flowed into the cavity using the hole, the solvent cleaning the cavity and then optionally being evacuated from the cavity. Specifically, the principles of the present invention may be used to clean the underfill space of a flip-chip package. The flip-chip package includes a packaging substrate with an evacuation port passing through the bulk of the packaging substrate such that the port is in communication with the underfill space and a bottom surface with the packaging substrate. This assembly is immersed in a solvent filled solvent bath. Solvent is drawn into the underfill space through said port. Alternatively, solvent may be injected into the underfill space through the port.

Abstract: An apparatus for mounting a heat sink to a chip package such as a BGA type chip package or the like is disclosed. In an exemplary embodiment, ground bumps are formed on the die substrate of the chip package and on the heat mating surface of the heat sink to be attached to the package. The ground bumps formed on the die protrude into the body of dimples formed in the body of the chip encapsulation package to make thermal/electrical ground contact with the ground bumps formed on the heat mating surface of the heat sink for electrically grounding the heat sink.

Abstract: A method and apparatus for generating a Fiber Channel compliant frame when a user enters a simple test pattern. A system is provided in which a user can enter an unencoded user test pattern for a Fiber Channel link which is being tested. The system then can then determine and combine additional information that will format the user's unencoded test pattern into a Fiber Channel compliant frame. The user can then visualize on a display the established Fiber Channel compliant frame and decide whether to modify the Fiber Channel compliant frame before outputting it to the link under test. A comparison can be performed between the data stream that is received after a transmission to the Fiber Channel link to determine whether the Fiber Channel link is in compliance with an established standard.

Abstract: A process-is disclosed for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where said trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as a stop layer in a CMP process to remove metal; and using this ARC layer as a stop layer to assist in removal of excess metal used to fill trenches and/or vias formed in the oxide layer. The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process to remove metal, than does the underlying oxide dielectric layer.

Abstract: A phase-locked loop circuit includes a voltage-controlled oscillator that includes a series circuit having a P-channel transistor, N-channel transistor, a third resistor and a first resistor connected in series in this order; a second resistor connected in parallel with a series circuit of the N-channel transistor and the third resistor; and an operational amplifier having its non-inverting input terminal connected to an output terminal of a lowpass filter, its inverting input terminal connected to a connected point of the third resistor and first resistor, and its output terminal connected to a gate of the N-channel transistor. The variable region of the resistance of the parallel circuit consisting of the N-channel transistor and the third and first resistors can be limited, which in turn enables the variable region of the control voltage of the voltage-controlled oscillator including a locking control voltage to be limited to a desired range.

Abstract: A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and reduced via poisoning characteristics. The composite layer of low k silicon oxide dielectric material is formed by depositing, in high aspect ratio regions between closely spaced apart metal lines, a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties until the resulting deposition of low k silicon oxide dielectric material reaches the level of the top of the metal lines on the oxide layer.

Abstract: A connector and pin structure for coupling with a higher density, finer conductor pitch ribbon cable or the like is disclosed. The connector has an array of pins disposed thereon where a beveled tip of the pin allows for the pin to penetrate the insulation sheath of a corresponding conductor, and the pins have a contacting structure that facilitates contact between the pin and the conductor. In one embodiment, such as where the conductor comprises a braided conductor, each pin has a bulge structure that allows for optimal contact between the pin and the conductor. In another embodiment, such as where the conductor comprises a braided conductor or a solid wire conductor, the pin is asymmetrical and has a notch structure that allows for optimal contact between the pin and the conductor.

Abstract: A horizontal deflecting optical waveguide is formed in an integrated circuit-like structure having a substrate and at least one layer of dielectric material above the substrate. A trench is formed in the dielectric material, and the trench has first and second portions angularly joined at a bent portion. A reflective layer of material adjoins, conforms to and extends along the side walls of the trench. A core of optically transmissive material conforms to the reflective layer within the trench. The reflective layer forms a wall at the bent portion which reflects light from the core located in one portion into the core located in the other portion.

Abstract: By turning OFF a PMOS transistor 15a of a feedback inverter 15 as the signal level at an input node 6 gradually changes from the “L” to “H” level, a high-level output from the feedback inverter 15 to an intermediate node 7 is limited, or by tuning OFF an NMOS transistor 15b of the feedback inverter 15 as the signal level at the input node gradually changes from the “H” to “L” level, a low-level output from the feedback inverter 15 to the intermediate node 7 is limited. Hence, the hysteresis width can be narrowed by limiting the output to the intermediate node 7 from the feedback inverter 15 which functions to expand the hysteresis width.

Abstract: The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array. A p-well 101 is formed in a surface of a substrate 10 and a channel forming semiconductor region 110 is defined in a surface of the p-well 101 and separated by a first n+ region 121 and a second n+ region 122. A carrier-supplying portion (CS: carrier supply) 111 is formed coming into contact with the first n+ region 121 and a carrier-acceleration-injection portion 112 (AI: acceleration and injection) is in contact with the second n+ region 122 in the channel forming semiconductor region 110 wherein the carrier-supplying portion 111 and carrier-acceleration-injection portion 112 are in contact with each other.

Abstract: The slew rate of a digital logic output signal delivered from an output pad of an integrated circuit is controlled relative to a load connected to the output pad. At least two pluralities of trigger signals at sequentially spaced time intervals are generated, and the time intervals between the first and second trigger signals or the temporal occurrence of the first and second trigger signals in relation to the load connected to the output pad is selected to change the slew rate of the output signal. The timing of the plurality of trigger signals is established in relation to an input signal to which the driver circuit responds and in relation to the change in the output signal with time as influenced by the load connected to the output pad.

Abstract: A signal is transmitted to/from an analog circuit portion and a digital circuit portion through an interface circuit portion. Analog circuit portion, digital circuit portion and interface circuit portion are externally supplied with power from different power supplies and provided in different well regions.

Abstract: A circuit and method for testing a transceiver. The circuit includes a bit pattern generator connected to the transceiver such that the bit pattern generator can communicate a serial data stream to a receiver portion of the transceiver. The circuit also includes a bit pattern checker connected to the transceiver such that a transmitter portion of the transceiver can communicate a serial data stream to the bit pattern checker. The transceiver is configured such that the receiver portion of the transceiver is communicatingly looped back to the transmitter portion of the transceiver such that a data stream can be communicated from the receiver portion of the transceiver to the transmitter portion of the transceiver. Desirably, a loopback circuit in connected to the transceiver and includes fixed bit pattern means for communicating at least one fixed bit pattern to the transmitter portion of the transceiver.

Abstract: A watchdog timer includes an instruction decoder, a delay circuit and a counter. The instruction decoder decodes a watchdog timer initialization instruction regularly executed to generate an instruction pulse for initializing the count of the counter. The delay circuit delays the rising edge of the instruction pulse, and supplies the delayed instruction pulse to the counter as a signal for initializing the count. The delay circuit prevents the pulse signal from being supplied to the counter when the operation frequency of the microcomputer is high or when the supply voltage to the microcomputer is low, so that the count of the counter overflows, and the overflow signal causes the microcomputer to be reset. This makes it possible to reset the microcomputer before it runs away, thereby solving a problem of a conventional watchdog timer in that the microcomputer can produce, if it runs away, an unexpected signal from its port before it is reset, and hence can impair the security of the system.

Abstract: The semiconductor cell library of the present invention includes a plurality of semiconductor cell definitions. At least one of the semiconductor cell definitions includes a base cell and at least one derivative cell. The base cell has a logical function and includes a base cell layout pattern of transistors with at least one diffusion. The derivative cell has the same logical function as the base cell and includes a derivative cell layout pattern of transistors with at least on a diffusion region. The diffusion region of the derivative cell layout pattern is expanded in one dimension outwardly from a geometric center of the layout pattern relative to the diffusion region of the base cell layout pattern.

Abstract: A graphical user interface is provided to represent relative and absolute physical locations of all RAID system components. Numerous graphical representations are defined. These graphical representations represent, in whole or in part, RAID system components such as disk drives, storage array controllers, controller and drive trays, power supplies, fans, software versions, hardware interfaces, connectors and/or cabling or wiring. The graphical representations are selected and arranged using a display screen. Their selection and arrangement are based on actual physical locations of their corresponding system components. The combined graphical representations can be used to check status of one or more system components, find and access the actual system components and/or update, either under user control or system control, the graphical representations to reflect any changes made to the corresponding actual RAID system components.

Abstract: A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a ligand is disclosed. One step of the method includes polishing a first side of the wafer in order to remove the ligand from the wafer. Another step of the method includes determining that a chelating agent has bound the ligand due to the polishing step removing the ligand of the polishing endpoint layer. The method also includes the step of terminating the polishing step in response to determining that the chelating agent has bound the ligand. A polishing system is also disclosed which detects a polishing endpoint based upon a chelating agent binding a ligand of a polishing endpoint layer of a semiconductor device.

Abstract: An integrated circuit having a die with one or more electrical input cells and one or more optical input cells. The cells are arranged together in an array, and the cells may have generally the same size and equivalent geographies, to permit standard electrical-only tools and practices to be used for designing the die.

Abstract: A process of inhibiting a corrosion of metal plugs formed in integrated circuits is described. The corrosion inhibiting process includes providing a partially fabricated integrated circuit surface including the metal plugs on a polishing pad to carry out chemical-mechanical polishing, introducing slurry including a corrosion inhibiting compound on the polishing pad in sufficient concentration to inhibit corrosion of the metal plugs of the partially fabricated integrated circuit surface, and polishing the partially fabricated integrated circuit surface.