Abstract: The present invention provides storage system controllers and methods of controlling storage systems therewith. The controller (10) includes a main processor (12), a memory (14), a device interface (18) adapted to interface a peripheral component (28-32), such as a RAID storage device, with the storage system controller, and an operations sequencer (24). The main processor sequences a plurality of tasks to be executed to complete an operation. The operations sequencer coordinates an execution of the plurality of tasks. Methods of the invention include receiving a task status for each of the plurality of tasks that is executed, and issuing an interrupt to the main processor after all of the plurality of tasks of the operation are finished executing. In this manner, the operations sequencer offloads at least some of the main processor overhead to improve processor efficiency.

Abstract: In order to smooth the entry into a debugging operation using a scan chain of registers in a microprocessor, a method for carrying out debugging procedures. The method comprises providing a processor with a chain of scan registers, a scan interface for interfacing with an external scan controller, a breakpoint interrupt mechanism for executing an interrupt instruction, and a processor clock control mechanism. The method includes detecting or generating a breakpoint in the operation of the processor. The breakpoint interrupt mechanism executes an interrupt instruction as a result of which the processor completes its current instruction, and signals the same to the scan interface. The scan interface asserts a Start Scan signal to the clock signal control mechanism, which whereupon stops the processor clock or clocks. The external scan controller is alerted to start a scan sequence.

Abstract: The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film.

Abstract: Digital circuitry synchronizes clock signals in a digital circuit. A value of a reference clock is sampled at a plurality of points near a transition point of a generated clock. It is determined whether the reference clock transitioned from a first state to a second state before, after or within an acceptable range of a transition point of the generated clock. Upon determining that the reference clock transitioned before the transition point of the generated clock, one period of the generated clock is shortened. Upon determining that the reference clock transitioned after the transition point of the generated clock, one period of the generated clock is lengthened.

Abstract: The system and method of the present invention for reducing the clock skew sensitivity of a shift register provides a control circuit for generating a clock signal to the first cell of the shift register. The first cell of the shift register receives the clock signal at its input and delays the clock signal for a specified time before transmitting the clock signal to the last cell in the shift register. The clock signal is propagated from the first cell of the shift register to the last cell of the shift register in a first direction. A test data circuit line is coupled to the last cell of the shift register. A test data signal is transmitted by the test data circuit line to the last cell of the shift register and is propagated through the shift register in a second direction, wherein the second direction is in a direction opposite from the direction of the clock signal.

Abstract: Apparatus and methods which allow multiple storage controllers sharing access to common data storage devices in a data storage subsystem to access a centralized intelligent cache. The intelligent central cache provides substantial processing for storage management functions. In particular, the central cache of the present invention performs RAID management functions on behalf of the plurality of storage controllers including, for example, redundancy information (parity) generation and checking as well as RAID geometry (striping) management. The plurality of storage controllers (also referred to herein as RAID controllers) transmit cache requests to the central cache controller. The central cache controller performs all operations related to storing supplied data in cache memory as well as posting such cached data to the storage array as required.

Abstract: A chemical-mechanical polishing apparatus for polishing a first side of a semiconductor wafer includes a polishing platen having a polishing surface. The apparatus also includes a wafer carrier assembly having a carrier body. The wafer carrier assembly is adapted to (i) engage the wafer by a second side of the wafer, and (ii) apply pressure to the wafer in order to press the wafer against the polishing surface of the polishing platen. The wafer carrier assembly is operable in a first carrier configuration and a second carrier configuration. A first fixture which is configured to apply pressure to the wafer at a first number of predetermined locations is secured to the carrier body when the wafer carrier assembly is operated in the first carrier configuration.

Abstract: A method of synthesizing integrated circuit (IC) design having DesignWare components comprising the steps of initially mapping DesignWare components, revising DesignWare component structure, ungrouping DesignWare components, and re-synthesizing DesignWare components. The step of initially mapping is performed using elaborate command and compile command of a logic synthesis tool. The step of ungrouping DesignWare components involves dissolving DesignWare modules to be merged with surrounding logic.

Abstract: A data serializer includes a differential output stage. The differential output stage has n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of n data inputs and n is an integer greater than one. Each pair of first and second control inputs is driven by a respective logic AND circuits having a rise time controlled by a first adjustable controlled current source and a fall time controlled by a second adjustable controlled current source.

Abstract: An electrostatic chuck, disposed within a processing chamber, receives a substrate and signals to selectively grip and release the substrate. A radio frequency power supply creates and passes a first signal to a first path that passes it to a high pass filter. The high pass filter inhibits signals lower than a first frequency from passing to the radio frequency power supply through the first path, and passes the first signal to a second path. The second path passes the first signal to a first electrode in the processing chamber, which emits the first signal within the processing chamber. A second electrode is also disposed within the processing chamber. The second electrode receives a second signal, and emits the second signal within the processing chamber. The emission of the first and second signals creates a plasma from the environment within the processing chamber.

Abstract: A method of detecting presence of a polishing slurry on a semiconductor wafer subsequent to polishing of the wafer includes the step of adding a chemical marker to the polishing slurry. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. In addition, the method includes the step of applying the polishing slurry to the first side of the wafer during the polishing step. Moreover, the method includes the step of ceasing the polishing step when the wafer has been polished to a predetermined level. Yet further, the method includes the step of directing incident electromagnetic radiation onto the wafer subsequent to the ceasing step. The method also includes the step of detecting a physical characteristic of resultant electromagnetic radiation which is produced in response to the incident electromagnetic radiation being directed onto the wafer.

Abstract: A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: A method for planarizing an integrated circuit on a substrate to a target surface of the substrate where at least portions of the target surface are of a first material having a first reflectivity. The substrate is overlaid with a top layer of a second material having a second reflectivity thereby forming an upper surface. Material is removed from the upper surface in a planarizing process, and the first reflectivity and second reflectivity of the upper surface are sensed with multiple wavelengths of electromagnetic radiation. The planarization process is stopped when a ratio of the second reflectivity to the first reflectivity equals a predetermined value.

Abstract: The present invention provides a semiconductor chip package with a fillet which contains a high percentage of a filler material by weight and a method of assembly with a semiconductor chip package for adding filler material to a non-filled or low-filled underfill system. The method of assembly produces a chip package where the concentration of filler material within the underfill material between the chip and the package substrate may be varied from location to location within the underfill material. The filler material increases the mechanical rigidity of the underfill material after it has hardened. Thus, using the approach of the present invention, the percentage of filler material may be increased in regions of the underfill material where the mechanical stresses require a greater mechanical rigidity. The present invention may be applicable to increasing the reliability of chip packages where the chip and the package substrate are separated by a gap about 25-50 microns wide.

Abstract: An input/output control circuit includes an input/output terminal, a first and second transistors configuring a CMOS circuit, a third transistor for carrying out a pull-up operation, an input control gate, an output control gate, a direction register for determining the direction of input/output direction, a control register for determining the mode of input or output, and a selection circuit connected to the gates for the first, second and third transistors, to the control terminals for the control gates, to the control register and also to the direction register. Since there is no redundant registers in this circuit construction, the whole size of the circuit can be made small, resulting in a reduction of total cost.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing respective data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: A method and apparatus for repairing and improving the endurance characteristics of process damaged oxide film formed in a semiconductor device involving sonic annealing by vibrating or oscillating a wafer at a predetermined frequency, wave amplitude, and duration. A signal from a frequency generator is amplified by a voltage amplifier and then sent to a speaker or other acoustic device for the production of vibrating acoustical wave energy. This acoustical wave energy is then directed at a submicron device wafer during a specified time period in order to anneal the gate oxide and, thereby, improve the characteristics of the oxide film.

Abstract: The present invention comprises methods and apparatus for determining the rate at which data was encoded when such data is received at a receiver. According to the present invention, the rate is determined by computing, for a plurality of possible rates, a final test statistic based on a plurality of measures. The final test statistics are compared and based upon certain selection criteria (for example, without limiting the foregoing, which final test statistic corresponds the highest value), the rate is selected. In the preferred embodiment, the measures comprise statistics based on the cyclical redundancy check, Viterbi metrics, re-encoded symbol error rate, and distance to next largest Viterbi metric.

Abstract: A microcomputer reset device includes a switching circuit for comparing, after a reset of a CPU is released during power-up, a reference voltage Vref with a second divided voltage Vd2 which is proportional to a supply voltage and is adjusted by the CPU, and for switching, when the second divided voltage Vd2 exceeds the reference voltage Vref, a clock source of the CPU from an internal clock signal to an external clock signal. This makes it possible to solve a problem of a conventional microcomputer reset device in that it is not unlikely that the microcomputer starts its operation before its reset has been completed, which hinders the normal operation of the microcomputer.