Abstract: A DRAM cell capacitor is described. Capacitor formation and cell isolation methods are integrated by using support sidewalls to form vertical DRAM capacitors. Doped polysilicon adjacent to the vertical sidewalls of the support provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that contacts and partially covers the doped polysilicon capacitor plate. Doped epitaxial silicon that contacts a portion of the dielectric forms the second capacitor plate and completes the DRAM capacitor.

Abstract: The AGC circuit is provided with an analog variable gain amplifying circuit which includes a plurality of fixed gain amplifiers and a selector for selecting one of the output signals of the plurality of fixed gain amplifiers, an A/D converter for receiving the selected output signal from the variable gain amplifying circuit, a digital band pass filter which allows only the burst signal and the color signal in the output signal from the A/D converter to pass through, and a digital AGC/detection circuit for controlling the gain of the variable gain amplifying circuit such that the burst signal remains stable and for amplifying the digital signal to obtain a digital output color signal such that the detected burst signal becomes equal in level to the digital reference signal. Thus, a more stable output signal can be obtained even with the variation in the ambient temperature or the power supply voltage.

Abstract: Provided is a vertically integrated (“chip-over-chip”) semiconductor package and packaging method. The invention provides higher packaging density and performance, including increased functionality, decreased signal propagation delays, improved circuit switching speed, lower thermal resistance and higher thermal dissipation measurements, relative to previous package designs. According to the invention, a semiconductor package may be composed of a flip chip (or chips) overlying one or more other flip chips, all electrically bonded to flip chip bond pads on a cavity-less semiconductor substrate. The upper and lower flips chips may be assembled in a variety of different configurations and may be thermally or electrically connected to each other. In a preferred embodiment, the flip chips, particularly the lower flip chip(s), are thinned so that the overall package height is within conventional ranges for traditional single chip packages.

Abstract: A digital-to-analog converter that is configured to implement a scaling scheme wherein a signal level is digitally scaled before a digital-to-analog converter, and is scaled back in the analog stage of the digital-to-analog converter. The scaling normalizes the input mean power to the digital-to-analog converter. Therefore, the digital-to-analog converter has a generally constant power and no extra dynamic range is needed. Preferably, the device is configured to receive fundamental, dedicated, supplemental and pilot channels, and is configured to combine the four channels to form a single signal. The single signal is then received by a gain scaler, a shaping filter, a digital-to-analog converter, and an analog filter. The gain scaler receives the signal, and applies a first gain thereto. Then, the shaping filter receives the signal, and the signal then travels to the digital-to-analog converter wherein a second gain is applied to the signal.

Abstract: A dual damascene type of structure of vias and trenches formed using layers of low k dielectric material is disclosed, and a process for making same without damage to the low k dielectric material during removal of photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings in the layers of low k dielectric material. Damage to the low k dielectric material is avoided by forming a first layer of low k dielectric material on an integrated circuit structure; forming a first hard mask layer over the first layer of low k dielectric material; forming over the first hard mask layer a first photoresist mask having a pattern of via openings therein; and then etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein, using an etch system which will also remove the first photoresist mask.

Abstract: The present invention is directed to a system and method for repairing degraded data. In a first aspect of the present invention, a method for patching degraded video data includes receiving a first frame of video data and decoding the first frame of video data so as to enable the first frame of video data to be displayed on a display device. A portion of the decoded first frame of video data that is degraded is identified. The degraded portion of the first frame of video data is patched utilizing a second portion of video data wherein the degraded portion of the first frame of video data is patched with the second portion of video data to enable the first frame of video data and the second portion of video data to be displayed concurrently. In a second aspect of the present invention, a video data patching apparatus includes a source decoder capable of accepting video data, the source decoder capable of decoding the video data so as to enable the video data to be displayed on a display device.

Abstract: An audio and video decoder for decoding audio, video and sub-picture streams in a disc player. The audio and video decoder has associated therewith a memory for storing commands and status information for each command. The audio and video decoder is responsive to commands received from a host to control audio and video decoding processes. The audio and video decoder includes a host interface and a command processor. The command processor includes a transfer mechanism for transferring commands received at a command buffer in the memory to a command FIFO in the memory and a status monitor for tracking an execution status of each command stored in the command FIFO and for updating a status word which is stored along with each command in the command FIFO. The command processor returns a pointer to the host for a unique address in memory for the status word for each command stored in the command FIFO.

Abstract: A system and method perform a two-pass fault simulation on an original design representation including a software-modeled design element and a hardware-modeled design element. Logic simulation generates input stimulus for a port on the boundary of the software-modeled design element and the hardware-modeled design element, where such ports are output ports of the software-modeled design element and input ports of the hardware-modeled design element. The input stimulus is merged with test patterns for the original design representation. A modified design representation is generated by replacing the software-modeled design element with a nonfunctional block. Most or all possible faults in the hardware-modeled design representation are seeded. The modified design representation is fault simulated in a first pass using the merged input stimulus and test patterns.

Abstract: The present invention is a simulation test program that incorporates a formatter which asks the simulator what, if anything has changed, rather than querying for all of the pin states and strengths at each iteration, i.e. at each time stamp. If nothing has changed in the current time stamp, then the time stamp is increased until a change which has occurred in the states of the pins is detected. Then the particular change is evaluated. This drastically reduces the runtime, memory usage, and output file size of the simulations.

Abstract: The present invention is directed to a system and method of compensating for coupling capacitance between bit lines in multi-port memories. The complementary bit lines are switched between a core cell and a modified core cell. The modified core cell may invert the connections to the access transistors. This results in the writing of data into the cell correctly while compensating for coupling capacitance.

Abstract: A digital logic circuit, such as a FIFO memory, includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a “2-hot” encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: A low temperature process is described for forming a low dielectric constant (k) fluorine and carbon-containing silicon oxide dielectric material for integrated circuit structures. A reactor has a semiconductor substrate mounted on a substrate support which is maintained at a low temperature not exceeding about 25° C., preferably not exceeding about 10° C., and most preferably not exceeding about 0° C. A low k fluorine and carbon-containing silicon oxide dielectric material is formed on the surface of the substrate by reacting together a vaporous source of a mild oxidizing agent, such as a vaporized hydrogen peroxide, and a vaporous substituted silane having the formula (CFmHn)—Si—(R)xHy wherein m is 1-3; n is 3-m; R is an alkyl selected from the group consisting of ethyl (—C2H5), methyl (—CH3), and mixtures thereof; x is 1-3; and y is 3-x.

Abstract: Methods and associated apparatus for generating and maintaining a unique identity for an enclosure in a storage system. Where an enclosure compliant with storage industry standards is to maintain a unique identity, methods of the present invention are operable to coordinate use of redundant devices within the enclosure that serve, among other functions, to store and report the unique identity of the enclosure. The redundant devices (i.e., environmental service cards or modules) assure that the enclosure identity remains unique among such enclosures despite hot or cold swaps of the redundant devices among the several enclosures. A change number portion of the unique identity value stored in each of the redundant devices is updated (i.e., incremented) each time a change in the configuration of redundant devices is detected by the devices. An incumbent one of the redundant devices reports the unique identity for the enclosure in response to attached system requests.

Abstract: A logic analyzer or a bus analyzer may be used to capture data from a source computer system to diagnose a problem arising in the source computer system. In many cases the problem can be traced to a particular hardware/software subsystem. Quite often, a customer of the manufacturer of the hardware/software subsystem maintains the source computer system. In the manufacturer's facilities is a reference system operated by a technician or engineer responsible to test and support the hardware/software subsystem. The source computer system and the reference system thus may involve different hardware and software configurations and possibly even different operating systems. The present invention provides a system and a method to allow data captured in a source computer system to be replayed in the remote reference system so as to recreate a captured event or analyze performance.

Abstract: A DRAM cell capacitor and access transistor are described. Capacitor formation, access transistor fabrication and cell isolation methods are integrated by using isolation trench sidewalls to form DRAM capacitors and access transistors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor. A vertically oriented access transistor is formed over top of the capacitor. To accomplish this, an isolation dielectric is deposited and patterned to provide a support structure for gate electrodes of the vertical access transistor above the trench sidewall capacitors.

Abstract: A memory array includes a zone of memory elements and a column multiplexer. The zone of memory elements is arranged in rows and columns, including a set of non-redundant columns and a redundant column. The column multiplexer has a section coupled to the set of non-redundant columns and to the redundant column. The column multiplexer has a selectable non-redundant path through the section for each of the non-redundant columns and a selectable redundant path for the redundant column. The redundant path is interchangeable with any one of the non-redundant paths.

Abstract: A method for improving the fault coverage of manufacturing tests for integrated circuits having structures such as embedded memories. In the disclosed embodiment of the invention, the integrated circuit die of a semiconductor wafer are provided with a fuse array or other circuitry capable of storing an identification number. The integrated circuit die also include an embedded memory or similar circuit and built-in self-test (BIST) and built-in self-test (BISR) circuitry. At a point early in the manufacturing test process, the fuse array of each integrated circuit die is encoded with an identification number to differentiate the die from other die of the wafer or wafer lot. The integrity of the embedded memory of each integrated circuit die is then tested at the wafer level under a variety of operating conditions via the BIST and BISR circuitry. The results of these tests are stored in ATE and associated with a particular integrated circuit die via the identification number of the die.

Abstract: A network comprises at least one host processing system, a number of storage controllers, each coupled to one of a plurality of storage arrays, each storage array including at least one mass storage device. Each storage controller may be coupled to at least one host processing system and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controller includes an interface with a host that emulates a mass storage device and an interface with a local storage array that emulates a host. The interfaces to the host and local storage arrays are independent of the type of host or devices in the local storage array. Two or more hosts may be dissimilar to each other, and two or more storage arrays may include dissimilar mass storage devices. Hosts access stored data using virtual addressing.

Abstract: A method and apparatus for accessing successive memory locations without the need for multiple index register writes and without the need for a wide address bus from the controller into a memory control system. The memory control system includes an index register and a data register. The index register has a connection to the controller and the buffer. The data storage register has a connection to the buffer and to the controller. The index register receives an address to a location in the buffer. Each time the contents of the index register are changed, data associated with the address are automatically written into the data storage register. Each time the data storage register is accessed (read or written), the index register in incremented. The controller is able to read or write unlimited numbers of sequential locations up to the full buffer space, using only a single controller access per byte.