Abstract: A vertically oriented metal circuit element is electrically connected and isolated between vertically separated conductors of interconnect layers in an integrated circuit. The methodology involves connecting a lower end of the metal element to the lower interconnect layer at the lower end of an opening in an inter-layer dielectric, preferably by simultaneously forming the metal element and connecting it to the conductor by vapor deposition. An upper end of the metal element initially extends above an upper surface of the inter-layer dielectric, and chemical mechanical polishing is employed to reduce the upper end to a level flush with the upper surface of the inter-layer dielectric. The flush upper end of the metal element allows it to be precisely spaced and covered with dielectric material to obtain predictable and reliable electrical isolation characteristics.

Abstract: A method and apparatus for accessing successive memory locations without the need for multiple index register writes and without the need for a wide address bus from the controller into a memory control system. The memory control system includes an index register and a data register. The index register has a connection to the controller and the buffer. The data storage register has a connection to the buffer and to the controller. The index register receives an address to a location in the buffer. Each time the contents of the index register are changed, data associated with the address are automatically written into the data storage register. Each time the data storage register is accessed (read or written), the index register in incremented. The controller is able to read or write unlimited numbers of sequential locations up to the full buffer space, using only a single controller access per byte.

Abstract: In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

Abstract: A phase interpolator that receives input clock phase and selection inputs that are distinct from the input clock phases. The phase interpolator generates an output clock phase based on the selection inputs. The phase interpolator includes selector devices which receive the input clock phases and receive the selection inputs, and includes cross-coupled switches which are connected to the selector devices and receive input clock phases therefrom. The selector devices select which input clock phases to provide to the cross-coupled switches based upon the selection inputs. The cross-coupled switches generate the output clock phase based upon the input clock phases which are received from the selector devices.

Abstract: A network comprises at least one host processing system, a number of storage controllers, each coupled to one of a plurality of storage arrays, each storage array including at least one mass storage device. Each storage controller may be coupled to at least one host processing system and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controller includes an interface with a host that emulates a mass storage device and an interface with a local storage array that emulates a host. The interfaces to the host and local storage arrays are independent of the type of host or devices in the local storage array. Two or more hosts may be dissimilar to each other, and two or more storage arrays may include dissimilar mass storage devices. Hosts access stored data using virtual addressing.

Abstract: A method and apparatus for manufacturing an electrostatic discharge protection device. A first gate structure for the electrostatic device is formed. A first lightly doped drain and a second lightly doped drain for the electrostatic discharge protection device is formed. A second gate structure for a data path transistor is formed. A third lightly doped drain and a fourth lightly doped drain for a data path transistor is formed, wherein the first lightly doped drain and the second lightly doped drain have a higher doping level relative to the third lightly doped drain and the fourth lightly doped drain.

Abstract: A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon carbide channel layer on the substrate. A silicon layer is formed on top of the strained silicon carbide channel layer. A gate insulation layer is formed on top of the silicon layer and strained silicon carbide channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode.

Abstract: An improved dual gate oxide process for dual-gated devices using oxygen ion implantation to vary the thickness of gate oxide layers. The desired layers are identified by photoresist layer patterning prior to an ion implantation. A subsequent heat treatment oxidizes the implanted region.

Abstract: An improved clock distribution system is provided for a multi block network having a series of independent blocks, with each independent block having an average load tap signal. The clock distribution circuit uses the load tap signal from the slowest independent block to synchronize the clock used in the remaining blocks. The clock for the subsequent block is tuned to the average load tap signal of the slowest block. The system clock system is incrementally delayed until it is in tuned with the average load tap signal of the slowest block, then if can be provided to the subsequent blocks of the network. The clock distribution system comprises sequential delay stages to incrementally delay the reference clock signal. The shift register controls each stage of delay, by enabling a multiplexer to allow the incrementally delayed reference clock signal to pass through.

Abstract: A transconductance continuous time filter circuit comprising a first differential pair of transistors (328 and 330), and at least one pair of tuning transistors (326 and 332). Each of the tuning transistors (326 and 332) may be coupled via a respective switching transistor (346 and 348) to a supply line, with the gate electrodes of the switching transistors (346 and 348) being coupled to a control line. The switching transistors (346 and 348) may be turned on or off to couple or uncouple the tuning transistors (326 and 332) from the first differential pair of transistors. The effective width of the differential pair may also be varied such that the transconductance and hence the cut-off frequency of the filter circuit.

Abstract: The invention provides a method for depositing a film on a surface of a semiconductor wafer while preventing formation of defects on the surface of the wafer. The method includes selecting a quartz wafer carrier for holding the semiconductor wafer during the depositing of the film, where the wafer carrier has quartz rods with fire-polished slots for receiving an edge of the semiconductor wafer. The semiconductor wafer is placed into the quartz wafer carrier with the edge of the wafer disposed within the fire-polished slots, and the wafer carrier and wafer are loaded into a deposition chamber. Air is evacuated from the deposition chamber, the temperature in the chamber is raised to a deposition temperature, the pressure within the deposition chamber is adjusted to a deposition pressure, and process gases are introduced to the deposition chamber. By reaction of the process gases, the film is deposited on the surface of the wafer and on the wafer carrier.

Abstract: In one embodiment, the present invention provides a storage system controller (10) having a main processor (12), a memory (14) and a device interface (18) adapted to interface with a peripheral component (28-32). The controller further includes an interrupt management scoreboard (24) adapted to receive a plurality of writes from the peripheral component(s) prior to interrupting the main processor. The main processor identifies a group of tasks to be executed, and sets up the scoreboard to await the completion of the tasks before interrupting the main processor.

Abstract: A demodulator circuit including: a signal generating circuit for generating a sine-wave signal and a cosine-wave signal whose frequencies are same as that of the carrier wave of a modulated signal, a multiplying circuit for multiplying the modulated signal by the sine-wave signal and the cosine-wave signal generated by the signal generating circuit, and a filtering circuit for eliminating the frequency twice as high as that of the carrier wave from each of the results of the computation conducted by the multiplying circuit. Due to this, no restriction is imposed by the frequency of the system clock signal in configuring the system as a whole.

Abstract: A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

Abstract: A short vertical channel, dual-gate, CMOS FET is fabricated by forming a plurality of channel segments in a starting material that extend longitudinally between source and drain areas. The channel segments are laterally separated from one another by spaces and are preferably formed from pillars of starting material located between the spaces. The pillars are laterally oxidized and the oxidation is removed to reduce the width of the pillars and form the channel segments. A gate structure is formed in the spaces between the channel segments. The width of each pillar is defined by conventional, contemporaneous photolithographic exposure and etching, but the width of each channel segment is substantially less than the width of the etch resistant barrier created photolithographically.

Abstract: A differential output buffer includes first and second complementary data inputs, an idle input, and a differential output stage having first and second output stage control inputs and first and second differential data outputs. First and second push-pull circuits charge one of the first and second output stage control inputs toward a logic high voltage and discharge the other of the first and second output stage control inputs toward a logic low voltage based on relative logic states of the first and second data inputs. A logic low voltage supply generator is coupled to the idle input and the logic low voltage supply terminal for setting the logic low voltage as a function of the idle input.

Abstract: To vigorously test synchronization logic and protocols in a digital circuit design, a synchronization logic model uses randomization to emulate the uncertainty in synchronization clock delay time exhibited in actual circuits. The synchronization logic model is inserted into a software description of the design so that simulation will reveal faulty assumptions in the synchronization protocol. Additionally, where a non-synchronized signal crosses from one clock domain to another clock domain in an asynchronous digital design, a transition on the non-synchronized signal triggers an “X” value window on the signal for a selected period relative to the receiving clock period, so that simulation will fail if the receiving logic samples the signal value during the “X” value window. These techniques aid in effective testing of the design.

Abstract: A dual threshold voltage sense amplifier that is capable of separating the rise time threshold from the fall time threshold, creating a dual sensing threshold voltage. In one embodiment of the invention, the dual threshold voltage sense amplifier is capable of providing a lower threshold for the rise time and a higher threshold for the fall time, thereby reducing the fall time and improving the read speed in asynchronous static memory without substantially increasing the core cell dimension or the overall design size.

Abstract: A low k carbon-doped silicon oxide dielectric material dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoresist mask; and wherein a second photoresist mask is subsequently used to form trenches in a second layer of low k carbon-doped silicon oxide dielectric material corresponding to a desired pattern of metal interconnects for an integrated circuit structure, followed by removal of the second photoresist mask.

Abstract: A method and apparatus are provided for restricting access to a digital video signal. According to the method, the digital video signal is encoded to produce an encoded video signal. In encoding the digital video signal, motion compensated encoding is performed on one or more first video picture portions of the digital video signal using a second video picture portion of the video signal as a reference for forming predictions. Only the second video picture portion of the encoded video signal is scrambled thereby producing a restricted access signal that is subsequently stored on a storage medium. Also provided is a method and apparatus for enabling access to a video signal. According to the method, the encoded video signal is received and only a first video picture portion of the video signal is descrambled. The encoded video signal is then decoded.