Abstract: A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the interconnect. A plurality of electronic "speed bumps" are spaced along the interconnect for disturbing or disrupting signals propagating along the interconnect toward the contact and thereby reducing undesirable back reflection and ringing. The speed bumps can include capacitance altering elements in the form of dielectric strips, or resistance altering elements in the form of low resistance doped areas or high resistance amorphous areas. The speed bumps can include first and second elements having different values of capacitance or resistance which are spaced along the interconnect in alternating relation.

Abstract: A method for cleaning solder bumps on a substrate that may be employed in a flip-chip design, for example, is described. The method of cleaning includes placing the substrate having the solder bumps into a plasma reactor, introducing a source gas including nitrogen trifluoride gas into the plasma reactor, striking a plasma from the source gas in the plasma reactor, and forming a fluoride compound on the surface of the solder bump.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclose. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A method of forming a metallization system in which ohmic contact is made to a silicon surface is described. A first layer of titanium is formed over the silicon surface. This first titanium layer is subsequently annealed in a nitrogen atmosphere to convert a first portion of the layer to a layer of titanium silicide, and a second portion to a first layer of titanium nitride. The titanium silicide layer provides for the formation of an ohmic contact between the metallization system and the silicon surface. The first titanium nitride layer provides for a degree of spike resistance between the silicon surface and the metallization system. A second layer of titanium nitride is formed over the first titanium nitride layer. This second titanium nitride layer provides further spike resistance between the silicon surface and the metallization system.

Abstract: An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first reduced from the prior art cell heights, and the width of the cell is then varied according to the particular need of the circuit. When the drive strength of the I/O circuit is high, and the circuit is more complicated, a wider cell is assigned. Conversely, for a circuit that is relatively simple, a narrower cell will be assigned. Each I/O cell has one associated bonding pad which is placed directly below the starting point of that cell. The height of the cells may also be varied on each side of the chip in order to be able to place more I/O cells along one or more sides or edges of the chip.

Abstract: A package for a semiconductor chip is provided which incorporates a plurality of levels of interconnect--conductive layers within the package which selectively direct signals to and from pins of the die and/or the pins of the package. A single general purpose chip may thus be fabricated in large quantities with the interconnect of the package used to define the specific purpose, functionality and pinout of the final device. Similarly, a standard package may be built to work with a large class of different chips and only the interconnect layers in the package need to be modified to allow the package to work with each different chip. In a second aspect of the invention, one or more layers of interconnect in the package may contain active electronic components which may be connected to nodes of the chip through the interconnect of the package and through the pins of the die.

Abstract: Electronic systems utilizing a plurality of integrated circuit packages having a stackable heat sink assembly is formed by press-fit assembly of two or more identical fin layers. Each fin layer is formed using powdered metallurgy and has a button-like projection extending from its bottom surface and a recess opening in its top surface. The button-like projection and recess opening are sized and shaped such that an interference fit is formed when the buttonlike projection of one fin layer is pressed into the recess of another fin layer. The use of an adaptor to increase or decrease the effective size of the button-like projection of the bottom-most fin layer is described. Relieving gases that may be entrapped in the recess during assembly is described. Circular, elliptical and polygonal shapes (outlines) for the fin layers are described.

Abstract: The handling of branch delay slots in MIPS microprocessors is enhanced. Branch instructions can be placed in branch delay slots by the judicious operation of the Exception Pointer Counter and the BD bit in the Cause register for exception handling.

Abstract: A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with the semiconductor device may be effected. The array of logic gates is linearly continuous and is unbounded along at least a first axis through to boundaries imposed an edge of the semiconductor wafer. The arrays of I/O circuit devices and connector pads are disposed adjacent, and in one embodiment parallel, to the array of logic gates. Integrated circuit structures including a customized number of individual logic gate elements may be easily provided by cutting a selected length from the strip-like portion of the array of logic gates. Requisite connector pad and I/O circuit features are provided by the adjacent arrays of I/O circuit devices and the adjacent array of connector pads.

Abstract: Field-effect transistors are formed on a substrate having silicided elements including diffusion (source and drain) regions and polysilicon gates. The silicided surfaces of these elements have low ohmic resistance and are used to provide interconnection between contacts that are spaced from each other, thereby freeing routing areas for other interconnections. The diffusion regions of adjacent transistors have edges that face each other, and are formed with indentations which constitute portions of a substrate tap area. The low ohmic resistance of the silicided surfaces of the diffusion regions enables the substrate tap area to be cut out of the diffusion regions without degrading the electrical performance of the transistors, thereby providing a substantial reduction in the space required for the transistors on the substrate.

Abstract: A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer.

Abstract: A substrate holder assembly for immobilizing an integrated circuit (IC) wafer during polishing is described. The substrate holder includes a base plate sized to support the integrated circuit (IC) wafer, a circumferential restraint member arranged with respect to the base plate to engage the IC wafer's edges and a carrier assembly disposed above the base plate and below the IC wafer. The carrier assembly includes a film having a surface that is characterized by a substantially oblate spheroid or hyperboloid surface of rotation, wherein the surface of the film is capable of supporting the IC wafer in a manner causing the IC wafer to bow according to the surface of rotation.

Abstract: According to the present invention, the invention relates to a semiconductor device having an activity monitor circuit formed thereon for monitoring the switching activity of signals generated by other circuits on the device during burn-in testing. In one embodiment, the activity monitor circuit includes means for detecting a present state of a signal; means for comparing the present state with a previous state of the signal; means for determining whether the state of the signal has switched a requisite number of times in a predetermined time period; and means for displaying the results of the determination.

Abstract: A semiconductor memory device which includes a word line, a bit line and a storage capacitor having first and second ends. A pair of FEATS each having gates coupled to the word line and one side coupled to the bit line. The other side of each FEAT is coupled to a storage capacitor upon which a selected one of four potential levels, corresponding to stored values of zero, one, two, or three, can be stored and thereafter read. One of the FEATS has a thicker gate oxide than the other and thus a higher threshold voltage. Voltage stored on the capacitor is read in two cycles thereby producing in the first cycle a high level pulse, a low level pulse, or no pulse and in the second cycle, a low level pulse or no pulse, depending upon the level of charge stored on the capacitor.

Abstract: An electronic system utilizing at least one semiconductor die having raised conductive bumps on its surface for connecting to other devices or systems is disposed on a face of a preformed planar structure (interposer) having through holes. Solder joints with conductive bumps on an underlying substrate are formed in the through holes. In one embodiment, the interposer is dissolvable. In another embodiment, the through holes are at least partially filled with a conductive material for electrically connecting to the die. In another embodiment, the through holes are angled so that the interposer acts as a pitch spreader or adapter. In another embodiment, ball bumps are disposed on a side of the interposer away from the die. In the electronic system, a semiconductor die may be disposed on a side of an optically transmissive preformed planar structure (interposer), and an optical element is disposed on an opposite side of the interposer.

Abstract: Described is a barrier layer in an integrated circuit structure which is formed in a via or contact opening over an underlying material in which diffusion of the underlying material (or filler material deposited over the barrier layer) through the barrier layer is inhibited without unduly increasing the thickness and resistivity of the barrier layer. This is accomplished by substituting an amorphous material for the crystalline titanium nitride to thereby eliminate the present of grain boundaries which are believed to provide the diffusion path through the titanium nitride material. In a preferred embodiment, the amorphous barrier layer comprises an amorphous ternary Ti--Si--N material formed using a source of titanium, a source of silicon, and a source of nitrogen. None of the source materials should contain oxygen to avoid formation of undesirable oxides which would increase the resistivity of the barrier layer.

Abstract: Techniques for computing power and delay values for macrocells in an ASIC design are described whereby the power or delay values are encoded as a multi-dimensional mathematical expression relating the power or delay value to the values of a plurality of operating conditions. The mathematical expression is derived from a multiple regression analysis of a plurality of power or delay sample values determined for a plurality of specific operating conditions. Delay values are derived directly from the mathematical relationship. Power dissipation values are determined by encoding current draw as a function of the various operating conditions. When a predicted current draw value is computed, it is multiplied by a value of power supply voltage to determine power dissipation.

Abstract: Techniques for providing semiconductor packages capable of forming connections to "high I/O" semiconductor dies is described, wherein there are at least two distinct pluralities of conductive lines. Leadframe-type packages and substrate-based package embodiments are described.

Abstract: A digital system utilizing at least one semiconductor integrated circuit die having positive mechanical alignment is provided between substrates using micro-bump contacts by forming "detented" conductive bump contacts on one substrate having a concave end which receive and align the generally convex contour of bump contacts on the other substrate. Various configurations of concavities and convexities are described. Flux may be disposed in the concave end of the detented bump contact to promote formation of joints between the concave and convex bump contacts. Both bump contacts may be formed of reflowable material, such as solder, or one or the other of the contacts may be formed of a non-reflowable material which may also function as a standoff between the two substrates. Each substrate is provided with a plurality of bump contacts, and one substrate may be provided with a combination of convex and concave bump contacts corresponding to concave and convex bump contacts on the other substrate.

Abstract: A power analysis tool includes a power arc identifier that extracts power arc information from simulation results including the occurrence time of each arc. These occurrence times are then stored in an arc occurrence database on which power analysis can be performed after the simulation has occurred. This allows a user to specify different circuit groupings on which to perform power analysis without requiring the circuit to be resimulated. The tool also includes a power calculator that converts average current, propagation delay, and intrinsic delay stored in a power data library into positive load current and negative load current for a cell. From these currents an "internal cell" current is derived which is related to the two load currents by a formula.