Patents Assigned to LSI
  • Low density parity check decoder with flexible saturation
    Patent number: 9048870
    Abstract: Embodiments of the present inventions are related to systems and methods for decoding data in an LDPC decoder with flexible saturation levels for variable node probability values.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: June 2, 2015
    Assignee: LSI Corporation
    Inventors: Shu Li, Zongwang Li, Shaohua Yang, Fan Zhang
  • Systems and methods for multi-stage encoding of concatenated low density parity check codes
    Patent number: 9048873
    Abstract: A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: June 2, 2015
    Assignee: LSI Corporation
    Inventors: Zongwang Li, Yu Kou, Chung-Li Wang, Shaohua Yang, Shu Li
  • Shift register-based layered low density parity check decoder
    Patent number: 9048867
    Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: June 2, 2015
    Assignee: LSI Corporation
    Inventors: Dan Liu, Qi Zuo, Chung-Li Wang, Zongwang Li, Lei Wang
  • Min-sum based hybrid non-binary low density parity check decoder
    Patent number: 9048874
    Abstract: An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor comprise different Galois fields. The field transformation circuit is operable to transform the variable node to check node messages from a first of the different Galois fields to a second of the Galois fields.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: June 2, 2015
    Assignee: LSI Corporation
    Inventors: Chung-Li Wang, Zongwang Li, Shu Li, Fan Zhang, Shaohua Yang
  • Systems and methods for multi-level encoding and decoding
    Patent number: 9047882
    Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate when decoding values encoded at a higher code rate.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: June 2, 2015
    Assignee: LSI Corporation
    Inventors: Lu Pan, Lu Lu, Haitao Xia
  • Three-position actuator for switchgear
    Patent number: 9048038
    Abstract: An actuator comprising: a disconnecting switch drive shaft; a first drive gear axially coupled to the drive shaft; a first follower gear in engagement with the first drive gear; a first drive disc having a first drive roller; a first rotary shaft axially supporting the first follower gear and the first drive disc; an earthing switch drive shaft; a second drive gear axially coupled to the earthing switch drive shaft; a second follower gear in engagement with the second drive gear; a second drive disc having a second drive roller; a second rotary shaft; a zeneva disc having a pair of groove portions which the first drive roller or the second drive roller is inserted into or separated from; and a main shaft for switching the disconnecting switch or the earthing switch in accordance with the rotation of the zeneva disc.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: June 2, 2015
    Assignee: LSIS Co., Ltd.
    Inventor: Sung Jun Tak
  • Pipelined vectoring-mode CORDIC
    Patent number: 9047148
    Abstract: Various embodiments of the present invention provide pipelined vectoring-mode CORDICS including a coordinate converter operable to yield a converted vector based on an input vector, wherein an x coordinate value of the converted vector is positive, a y coordinate value of the converted vector is positive, and the x coordinate value is greater than or equal to the y coordinate value, a pipeline of vector rotators operable to perform a series of successive rotations of the converted vector to yield a rotated vector and to store rotation directions of the series of successive rotations, and at least one lookup table operable to yield an angle of rotation based on the rotation directions.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: June 2, 2015
    Assignee: LSI Corporation
    Inventors: Zhibin Li, Yao Zhao
  • Control circuit for electric power circuit switch
    Patent number: 9048657
    Abstract: A control circuit for an electric power circuit switch includes: a sampling/hold circuit section configured to sample a period of a detection signal of a current of an electric power system and provide a sampled signal; a discrete Fourier transforming (abbreviated as DFT) circuit section perform DFT on the one-period sampled signal to provide a magnitude and a phase of a frequency component of the current of the electric power system; a differentiator configured to differentiate the detection signal to provide a rate of change of the current over time; and a controller to determine whether to perform trip controlling according to the magnitude of the frequency component of the current from the DFT circuit section or the rate of change from the differentiator on the basis of the rate of change of the current and the reference rate of change.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: June 2, 2015
    Assignee: LSIS Co., Ltd.
    Inventor: Young Woo Jeong
  • Memory device having control circuitry for write tracking using feedback-based controller
    Patent number: 9047936
    Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory array. The feedback-based controller generates a reset signal for application to a reset input of the write signal generation circuitry at least in part as a function of a logic level transition delay of a selected one of the first and second internal nodes of the dummy memory cell.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: June 2, 2015
    Assignee: LSI CORPORATION
    Inventors: Vikash, Kamal Chandwani, Rahul Sahu
  • POLLING METHOD OF COMMUNICATION SYSTEM
    Publication number: 20150149665
    Abstract: The present disclosure relates to a polling method of communication system configured to reduce a polling time by receiving responses from a plurality of auxiliary devices using one time of response request signal by a main device during polling, the method including, requesting, by a main device, transmission of response request signals from a plurality of auxiliary devices connected to the main device (request step), determining whether each of the plurality of auxiliary devices is a response object after receiving the response request signal (response object determination step), determining a response order by each of the plurality of auxiliary devices that has determined itself as the response object (response order determination step), and responding, by itself, to the response request after lapse of waiting time in response to its response order (response step).
    Type: Application
    Filed: October 22, 2014
    Publication date: May 28, 2015
    Applicant: LSIS CO., LTD.
    Inventor: KMM KI PAEK
  • REPEATER FOR POWER LINE COMMUNICATION AND REPEATING METHOD THEREOF
    Publication number: 20150146764
    Abstract: The present disclosure relates to a repeater for power line communication, capable of preventing a ping-pong phenomenon and a loss of data packet and improving communication reliability and communication speed by allowing a power line communication terminal to add its repeater number in a received data packet for transmission, and a repeating method thereof.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 28, 2015
    Applicant: LSIS CO., LTD.
    Inventors: Jae Shik YOON, Dong Sun WON
  • ELIMINATING OR REDUCING PROGRAMMING ERRORS WHEN PROGRAMMING FLASH MEMORY CELLS
    Publication number: 20150149698
    Abstract: Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur.
    Type: Application
    Filed: December 3, 2013
    Publication date: May 28, 2015
    Applicant: LSI CORPORATION
    Inventors: Yu Cai, Yunxiang Wu, Zhengang Chen, Erich Haratsch
  • Flash Channel With Selective Decoder Likelihood Dampening
    Publication number: 20150149871
    Abstract: An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.
    Type: Application
    Filed: November 29, 2013
    Publication date: May 28, 2015
    Applicant: LSI Corporation
    Inventors: Zhengang Chen, Yunxiang Wu, AbdelHakim S. Alhussien, Erich F. Haratsch
  • Integrated Frequency Multiplier and Slot Antenna
    Publication number: 20150145740
    Abstract: A metal substrate with a slot therein forms a slot antenna, the slot having a major axis and a minor axis. A dielectric layer has a plurality of terminals disposed on or in the dielectric layer and the layer is attached on one surface of the substrate. The terminals of a non-linear device, such as a diode, are connected to corresponding terminals of the dielectric layer. The non-linear device is positioned proximate the slot and is substantially aligned with a minor axis of the slot. A transmission line feeds an RF signal to the non-linear device that in turn frequency multiplies the RF signal to an RF signal that is radiated by the slot antenna. The dielectric layer is positioned in the slot such that the radiated RF signal has a desired output power. A protective layer is applied to the other surface of the substrate to cover the slot.
    Type: Application
    Filed: December 18, 2013
    Publication date: May 28, 2015
    Applicant: LSI Corporation
    Inventors: Roger A. Fratti, Albert Torressen, James R. McDaniel, Scott W. McLellan
  • Read Retry For Non-Volatile Memories
    Publication number: 20150149840
    Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
    Type: Application
    Filed: December 20, 2013
    Publication date: May 28, 2015
    Applicant: LSI Corporation
    Inventors: AbdelHakim S. Alhussien, Erich F. Haratsch, Sundararajan Sankaranarayanan, YingQuan Wu
  • BIT-LINE DEFECT DETECTION USING UNSATISIFIED PARITY CODE CHECKS
    Publication number: 20150149855
    Abstract: An apparatus having a device and a circuit is disclosed. The device has a plurality of bit-lines and is configured to store a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword and (iii) generate a map of defects according to the syndrome. Each of a plurality of bits in the map corresponds to a respective one of the bit-lines.
    Type: Application
    Filed: December 9, 2013
    Publication date: May 28, 2015
    Applicant: LSI Corporation
    Inventors: AbdelHakim S. Alhussien, Erich F. Haratsch, Earl T. Cohen
  • INCREMENTAL UPDATES FOR ORDERED MULTI-FIELD CLASSIFICATION RULES WHEN REPRESENTED BY A TREE OF LONGEST PREFIX MATCHING TABLES
    Publication number: 20150149395
    Abstract: An apparatus includes a memory and a processor. The memory may be configured to store at least a portion of a multi-level tree representation of an ordered multi-field rule-based classification list. The tree representation includes at least one non-leaf level and one or more leaf levels. Each entry in the at least one non-leaf level contains a count value indicating a number of rules having a matching field. Entries in at least one of the one or more leaf levels include rule pointers arranged in priority order. The processor may be configured to incrementally insert or delete rules, while preserving ordering semantics of the tree representation.
    Type: Application
    Filed: December 5, 2013
    Publication date: May 28, 2015
    Applicant: LSI Corporation
    Inventors: Narender R. Vangati, Rajarshi Bhattacharya
  • DECODING WITH LOG LIKELIHOOD RATIOS STORED IN A CONTROLLER
    Publication number: 20150149856
    Abstract: An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values.
    Type: Application
    Filed: December 20, 2013
    Publication date: May 28, 2015
    Applicant: LSI Corporation
    Inventors: Yunxiang Wu, Zhengang Chen, Erich F. Haratsch
  • Arc extinguishing apparatus for ring main unit
    Patent number: 9040861
    Abstract: An arc extinguishing apparatus for a ring main unit includes: a housing; a plurality of fixed contactor assemblies fixed to be protruded toward the center in the housing and formed by inserting a permanent magnet for arc extinguishing by a magnetic force between a pair of main circuit fixed contacts; a plurality of earthing fixed contactors fixed to be protruded toward the center in the housing and installed to be spaced apart from the fixed contactor assemblies at a predetermined angle; a 3-phases common rotational shaft installed to be rotatable at the center of the housing; and a rotatable movable contactor assembly having a plurality of puffer guide plate sections having openings with a narrow opening width to accelerate the velocity of flow of insulating gas to extinguish arc by blowing it, and rotatable to a circuit closing position, an earthing position, and a circuit opening position.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: May 26, 2015
    Assignee: LSIS Co., Ltd.
    Inventor: Woo Jin Park
  • Lighting
    Patent number: D730557
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: May 26, 2015
    Assignee: LSI Industries, Inc.
    Inventors: John D. Boyer, Daniel Hutchens, Eric Jon Mooar