Patents Assigned to LSI
  • Solar power inverter with sealing means
    Patent number: 9040820
    Abstract: A solar power inverter having a sealing means includes: a main case having an opening on a front surface thereof, the opening open and closed by a main cover; an auxiliary case coupled to one side surface of the main case, and having a second opening on a front surface thereof, the second opening open and closed by an auxiliary cover; and a gasket interposed between the main case and the auxiliary case, wherein the main case and the auxiliary case are coupled to each other by coupling bolts which pass through the main case, the gasket and the auxiliary case.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 26, 2015
    Assignee: LSIS Co., Ltd.
    Inventor: Hyuk Il Kwon
  • Systems and methods for variable redundancy data protection
    Patent number: 9043684
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: May 26, 2015
    Assignee: LSI Corporation
    Inventors: Shaohua Yang, Lav D. Ivanovic, Fan Zhang, Douglas M. Hamilton
  • Electrode assembly for vacuum interrupter
    Patent number: 9040862
    Abstract: An electrode assembly for a vacuum interrupter is configured such that supporting members can support most of a contact electrode plate and a supporting electrode plate in an axial direction with coil conductors interposed therebetween. Accordingly, an impact generated between electrode assemblies upon a closing operation of the vacuum interrupter may be evenly distributed onto the supporting members, which may result in preventing each of the electrode plates and the coil conductors from being deformed. Also, the supporting members are inserted into the electrode plates and the coil conductors, thereby effectively preventing a current from flowing via the supporting members. In addition, the supporting member may be wide and large so as to simplify an assembly operation and reduce an assembly time.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 26, 2015
    Assignee: LSIS Co., Ltd.
    Inventor: Jae Seop Ryu
  • Program module applicability analyzer for software development and testing for multi-processor environments
    Patent number: 9043770
    Abstract: In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: May 26, 2015
    Assignee: LSI Corporation
    Inventors: Pavel Aleksandrovich Aliseychik, Petrus Sebastiaan Adrianus Daniel Evers, Denis Vasilevich Parfenov, Alexander Nikolaevich Filippov, Denis Vladimirovich Zaytsev
  • I/O REQUEST MIRRORING IN A CLUSTERED STORAGE SYSTEM
    Publication number: 20150143164
    Abstract: Clustered storage systems and methods are presented herein. One clustered storage system includes a logical volume comprising first and second pluralities of storage devices. The first plurality of storage devices is different from the second plurality of storage devices and includes at least the same data as the second plurality of devices. The storage system also includes a first storage node operable to process first I/O requests to the first plurality of storage devices and a second storage node communicatively coupled to the first storage node and operable to process second I/O requests to the second plurality of storage devices. An I/O request of the first I/O requests initiates a redirection condition that the first storage node detects. Then, based on the redirection condition, the first storage node directs the second storage node to process data of the I/O request.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: LSI CORPORATION
    Inventors: Sridhar Rao Veerla, Naveen Krishnamurthy
  • CIRCUIT BREAKER WITH INPUT LOAD INCREASING MEANS
    Publication number: 20150137916
    Abstract: A circuit breaker comprises a switching mechanism that including a linkage with a drive joint that is mounted to be rotatable around a rotation axis by a driving force, wherein, during the ON operation, an axis formed by the rotation axis and the point of action of the driving force makes an acute angle with the line of action of the driving force, so that the drive joint causes the tangential force of the driving force to act as input load, at least one hinge part of the linkage is configured in a way that the connecting pin is movably hinged to the long hole-shaped hinge hole, and at least one hinge part of the linkage causes the tangential force to increase by changes in the acute angle as the connecting pin moves from a first side of the long hole-shaped hinge hole to a second side.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 21, 2015
    Applicant: LSIS CO., LTD.
    Inventors: Seong Yeol CHO, Jae Kwan SEO
  • MAIN CIRCUIT PART OF VACUUM CIRCUIT BREAKER WITH SELF-POWERED TEMPERATURE SENSOR ASSEMBLY
    Publication number: 20150139275
    Abstract: The present invention relates to a main circuit part of a vacuum circuit breaker, and more particularly, to a main circuit part of a vacuum circuit breaker with a temperature sensor. The main circuit part of a vacuum circuit breaker with a self-powered temperature sensor assembly includes: a self-powered temperature sensor module; and a support bracket enclosing and supporting the self-powered temperature sensor module.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 21, 2015
    Applicant: LSIS CO., LTD.
    Inventors: Woo Jin PARK, Min Kyu SEO
  • PRE-CHARGING CIRCUIT OF INVERTER
    Publication number: 20150138849
    Abstract: A pre-charging circuit of inverter is disclosed, the pre-charging circuit of inverter including a relay arranged between an output node of the rectifier and an input node of the DC-link capacitor, and a pre-charging resistor arranged between an output node of the rectifier and an input node of the inverter unit, whereby a degree of freedom for PCB design can be obtained.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 21, 2015
    Applicant: LSIS CO., LTD.
    Inventors: Tae Suk BAE, Jae Moon LEE
  • APPARATUS AND METHOD FOR DETECTING OUTPUT PHASE DEFICIENCY IN INVERTER
    Publication number: 20150138854
    Abstract: An apparatus and a method for detecting phase deficiency in an inverter is provided, the method including deciding whether a sector of the output current is a sector where current detection is possible based on switching operation status of the switching element in the inverter, maintaining a phase deficiency variable when deciding the current detection in the sector of the output current to be impossible, adding a count to a phase deficiency variable to accumulate when deciding the current detection in the sector of the output current to be possible and deciding the output current to be within a phase deficiency band, and determining as phase deficiency when the phase deficiency variable is greater than a prescribed detection level.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 21, 2015
    Applicant: LSIS CO., LTD.
    Inventors: Jae Moon LEE, Tae Suk BAE
  • CIRCUIT BREAKER
    Publication number: 20150136578
    Abstract: A circuit breaker includes: fixed contact points; and a moving contact assembly. The moving contact assembly includes: a shaft; a moving contact that is held in the shaft; and springs that apply torque to the moving contact. The shaft includes: stopping faces that are formed in a direction opposite to the direction in which the moving contact rotates; and guiding faces that are curved from the stopping faces. The moving contact includes: first surfaces that are formed on the radius of rotation of the moving contact; and sliding surfaces that are located at an angle to the first surfaces and slanted toward the center of rotation with respect to the line of action of a tangential force of torque at the points of contact with the guiding faces.
    Type: Application
    Filed: October 27, 2014
    Publication date: May 21, 2015
    Applicant: LSIS CO., LTD.
    Inventor: Ki Hwan OH
  • APPARATUS FOR CONTROLLING PARALLELED INVERTER
    Publication number: 20150138855
    Abstract: An apparatus for controlling paralleled inverter is disclosed. In the apparatus for controlling paralleled inverter, one synchronization signal is shaped by at least two inverters to respectively transmit a voltage command and an operation command.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 21, 2015
    Applicant: LSIS CO., LTD.
    Inventor: Jong Je PARK
  • Systems and Methods for FAID Follower Decoding
    Publication number: 20150143196
    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for decoding information.
    Type: Application
    Filed: December 10, 2013
    Publication date: May 21, 2015
    Applicant: LSI Corporation
    Inventors: Yequn Zhang, Yang Han, Yu Chin Fabian Lim, Shu Li, Fan Zhang, Shaohua Yang
  • APPARATUS FOR CONTROLLING SPEED IN RAILWAY VEHICLES
    Publication number: 20150142226
    Abstract: An apparatus for controlling speed in railway vehicles is disclosed, the apparatus estimates a future train speed and determines a control input (first speed control) configured to control a train speed based on a TTSLC {Time-To-Speed-Limit Crossing, a time taken by a train from a current time to exceed an ATP (Automatic Train Protection) speed profile, which is an ATP speed limit}, and determines a control input (second speed control) configured to control the train speed based on a difference between the ATP speed profile and an actual train speed, whereby the first speed control or the second speed control is selected in response to the TTSLC and outputted to the train.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Applicant: LSIS CO., LTD.
    Inventors: Jongchul JUNG, Yong Gee CHO
  • FAULT CURRENT LIMITER
    Publication number: 20150138683
    Abstract: A fault current limiter is provided. According to an embodiment of the present disclosure, the fault current limiter includes a switch whose contact point is opened when a fault current occurs; a current limiting element configured to limit the fault current when the fault current occurs; and a diode being serial-connected to the current limiting element, wherein a breakdown voltage of the diode is higher than a voltage drop by an impedance of the switch when a normal current flows.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 21, 2015
    Applicant: LSIS CO., LTD.
    Inventors: Jung Wook SIM, Gyeong Ho LEE, Hae Yong PARK
  • INTERLEAVED WRITE ASSIST FOR HIERARCHICAL BITLINE SRAM ARCHITECTURES
    Publication number: 20150138863
    Abstract: An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: LSI CORPORATION
    Inventors: Rajiv Kumar Roy, Donald Albert Evans, Rasoju Veerabadra Chary, Rahul Sahu
  • GLOBAL BITLINE WRITE ASSIST FOR SRAM ARCHITECTURES
    Publication number: 20150138876
    Abstract: An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the memory cell segments via the local bitlines for writing to the memory cells. The SRAM device further includes a global input/output module operable to hold the global bitline at logical zero, to toggle the global bitline to logical one when data is to be written, to select one of the segments of memory cells for writing after the global bitline has been toggled, and to toggle the global bitline to logical zero when data is written to the selected memory cell segment to provide a negative boost voltage to the local bitline of the selected memory cell segment.
    Type: Application
    Filed: January 13, 2014
    Publication date: May 21, 2015
    Applicant: LSI CORPORATION
    Inventors: Rajiv Kumar Roy, Rasoju Veerabadra Chary
  • Systems and Methods for Soft Decision Generation in a Solid State Memory System
    Publication number: 20150143202
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory.
    Type: Application
    Filed: December 16, 2013
    Publication date: May 21, 2015
    Applicant: LSI Corporation
    Inventors: Zhengang Chen, Yunxiang Wu, Erich F. Haratsch
  • MEMORY ARCHITECTURE WITH ALTERNATING SEGMENTS AND MULTIPLE BITLINES
    Publication number: 20150138864
    Abstract: Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: LSI CORPORATION
    Inventors: Donald Albert Evans, Rasoju Veerabadra Chary, Rajiv Kumar Roy, Rahul Sahu
  • Current To Voltage Converter
    Publication number: 20150137855
    Abstract: An apparatus for converting current to voltage includes a pair of current inputs, a differential voltage output connected to the pair of current inputs, a current summing node connected to the pair of current inputs through a first resistor branch, a common mode feedback node connected to the pair of current inputs through a second resistor branch, an amplifier operable to generate a current control signal based at least in part on a voltage at the common mode feedback node, and a current controller operable to control a current through the current summing node based at least in part on the current control signal.
    Type: Application
    Filed: January 2, 2014
    Publication date: May 21, 2015
    Applicant: LSI Corporation
    Inventors: Dong Hui Wang, Zheng Xin Cao, Shu Dong Cheng, Yan Xu, Jie Hao Xu, Ming Chen
  • Apparatus for protecting analog input module from overvoltage
    Patent number: 9036313
    Abstract: Disclosed is an apparatus for protecting an analog input module from overvoltage, the apparatus including an analog input module and a stabilization unit. The analog input module converts one of a plurality of positive/negative analog signals inputted from the outside thereof into a digital signal and insulates the converted digital signal. The stabilization unit supplies voltages of the positive/negative analog signals to the analog input module when the voltage levels of the plurality of positive/negative analog signals are higher than the levels of positive/negative operating voltages in the analog input module.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: May 19, 2015
    Assignee: LSIS Co., Ltd.
    Inventor: Jae Il Kwon