Abstract: An apparatus for low density parity check decoding includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node messages and to calculate checksums based on the variable node to check node messages, and a scheduler operable to determine a layer processing order for the variable node processor and the check node processor based at least in part on the number of unsatisfied parity checks for each of the H matrix layers.

Abstract: A method and system for self-sizing dynamic cache for virtualized environments is disclosed. The preferred embodiment self sizes unequal portions of the total amount of cache and allocates to a plurality of active virtualized machines (VM) according to VM requirements and administrative standards. As a new VM may emerge and request an amount of cache, the cache controller reclaims currently used cache from the active VM and reallocates the unequal portions of cache required by each VM. To ensure cache availability, a quick reclamation amount of cache is immediately available to each new VM as it makes the request begins operation. After reallocation, the newly created VM may rely on a guaranteed minimum quota of cache to ensure performance.

Abstract: The present inventions are related to systems and methods for decoding data in an LDPC layer decoder for LDPC codes with overlapped circulants.

Abstract: A channel equalization scheme is provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid receiver equalizer. The hybrid receiver equalizer controls crosstalk while maintaining signal bandwidth and linearity of a signal by the high-order high frequency roll-off of the linear equalizer used. Using this configuration, the hybrid receiver equalizer eliminates the need for adaptive bandwidth controller used in conventional low-pass receiver equalization schemes. The hybrid receiver equalizer can be used in receivers for dual-speed simultaneous transmission on the same physical link.

Abstract: Methods and structure for determining compatibility between a pair of SAS devices for support of super-standard features of the devices. Features and aspects hereof provide for exchange of information between a first and second SAS device using SAS protocol in non-standard manners. The exchanges are designed to exchange information between compatible, enhanced device without causing protocol violation errors in either the first or second devices. The information exchanged represents super-standard features supported by each device. Mutually supported super-standard features are enabled for further communications between the devices. If no super-standard features are mutually supported or if the second device is non-enhanced, no super-standard features are enabled in further communications between the devices.

Abstract: An inverter device may include a converter unit configured to receive single phase AC power to output DC power; a capacitor unit configured to absorb the DC power; an inverter unit configured to synthesize the absorbed DC power to output the drive power of a load; and a converter controller configured to control the converter unit based on the AC power and the output DC power of the converter unit, wherein the converter controller includes a converter gate signal generator configured to control a plurality of gates contained in the converter unit; and an input line harmonic voltage generator configured to output converter additional power having a predetermined multiple of the frequency of the fundamental frequency component of the AC power with the same size as that of the fundamental frequency component of the AC power to an adder connected to the input side of the converter gate signal generator.

Abstract: A flexible shunt for a vacuum circuit breaker can have a reduced straight length and improved flexibility even with an increased thickness within a predetermined accommodation space of a main circuit part. The flexible shunt comprises a pair of conductive plates, each including a clamp connecting portion configured as a flat conductive member, the clamp connecting portion being connected the clamp, a terminal side connecting portion configured as a flat conductive member, the terminal side connecting portion being connected to the terminal side, and a flexible curved portion configured to connect the clamp connecting portion to the terminal side connecting portion, the flexible curved portion being formed to be projected outwardly.

Abstract: The disclosure is directed to a system and method of a system and method for determining fundamental bit cell duration of a data record, which can be used for pattern-dependent write (PDW) current control. According to various embodiments of the disclosure, at least a first portion of a data record is fed through a plurality of delay units. A binary output of each delay unit is stored in at least one register when the delay units have received the first portion of the data record. The register contents are then decoded to determine fundamental bit cell duration of the data record based upon the stored binary outputs.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.

Abstract: A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR.

Abstract: An apparatus for calculating a speculative bit error rate includes a data decoder operable to iteratively decode received data to yield decoded data, and a speculative bit error calculator operable to calculate a bit error rate based on the decoded data and the received data while the data decoder is decoding the received data. The bit error rate is updated with each decoding iteration in the data decoder.

Abstract: A memory device includes a memory array having a plurality of memory cells each having first and second power supply nodes, first and second virtual power supply nodes, a latch circuit, and a write assist circuit. The latch circuit includes a first and second inverters in a cross-coupled inverter configuration. The first inverter is connected between the first virtual power supply node and the second power supply node, and the second inverter is connected between the second virtual power supply node and the second power supply node.

Abstract: A magnetic device is provided. The magnetic device includes a bobbin including a hollow portion extending in a longitudinal direction, coils wound around the outside of the bobbin, a core coupled to the bobbin outside the bobbin. The bobbin includes a first winding portion around which the coil is wound, a second winding portion which is disposed at one side of the first winding portion in the longitudinal direction, and around which the coil is wound, a tolerance relief part disposed between the first and second winding portions, coupling parts symmetrically disposed to each other on the outsides of the first and second winding portions, respectively. The tolerance relief part is elastically deformable in the longitudinal direction.

Abstract: Provided is a synthetic test circuit for synthetic-testing a thyristor valve in high voltage direct current (HVDC). A resonant circuit applies forward DC current, a reverse DC voltage, and a forward DC voltage to synthetic-test the thyristor valve. A current generation unit generates DC current that is above a reference current value to supply the generated DC current into the resonant circuit. A voltage generates unit generating a DC voltage that is above a reference voltage value to supply the generated DC voltage into the resonant circuit. The resonant circuit includes a charging auxiliary valve for charging a gate driver of the thyristor valve.

Abstract: A door interlock device for a power transformer room in a vacuum circuit breaker includes a cam disposed on a shaft of a ground switch, a supporter disposed on a side plate of a power transformer room, a shaft disposed at the supporter to be slidable and having one end contacting the cam to be upward and downward movable, a spring disposed within the supporter to provide an upward elastic force to the shaft, and an interlock plate disposed at one side of the power transformer room door and configured to be in contact with the shaft.

Abstract: One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.

Abstract: Disclosed is an event input module, wherein the event input module receives time information which is an IRIG-B signal of a predetermined method from an outside time provider, allocates the time information to a detected event and determines event generation information.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.

Abstract: A first I/O transaction request is sent to a storage controller for processing by firmware running on the storage controller. A second I/O transaction request is sent to storage hardware without further processing by the firmware running on the storage controller. Since the firmware did not process the second I/O transaction request, information associated with the second I/O transaction is stored in in a circular buffer accessible to the firmware running on the storage controller. The firmware running on the storage controller reads, from the circular buffer, the information associated with the second I/O transaction that was stored in the circular buffer.

Abstract: Methods and structure for reduced layout congestion in a switching device integrated circuit. A switching device such as a Serial Attached SCSI (SAS) expander comprises a switching circuit to couple any of a plurality (“N”) of physical links of the switching device with any other physical link of the switching device. The switching circuit comprises a first stage circuit adapted to couple any of the N physical links with a selected one of N/2 communication paths of the switching circuit and comprises a second stage circuit adapted to couple any of the N/2 communication paths with any of the N physical links. Since only N/2 communication paths may be active at any time in such a switching device, a control unit of the switching device tracks which of the N/2 communication paths are presently in use or unused so that an unused path may be selected for a new connection.