Abstract: In certain embodiments, a slave clock node in a wireless packet network achieves time synchronization with a master clock node by implementing a packet-layer synchronization procedure, such as the IEEE1588 precision timing protocol (PTP), to set the slave's local time based on the master's time. The slave's local time is then maintained by implementing a physical-layer syntonization procedure, such as synchronous Ethernet, without relying on the packet-layer synchronization procedure. The packet-layer synchronization procedure may be selectively employed to adjust the slave's local time (if needed) after significant periods of time (e.g., substantially greater than one second). Both the packet-layer synchronization procedure and the physical-layer syntonization procedure are traceable to a common reference timescale (e.g., UTC). Depending on the implementation, the packet-layer synchronization procedure can be, but does not have to be, terminated when not being employed to adjust the slave's local time.

Abstract: Disclosed is an apparatus for controlling an IPMSM, the apparatus according to exemplary embodiments of the present disclosure including a first generating unit generating a q-axis reference voltage of a synchronous reference frame from a reference frequency, a current converter generating a current of the synchronous reference frame from a 3-phase current of the IPMSM, and a voltage controller generating a d-axis reference voltage compensating a voltage in response to a load change.

Abstract: A RAID data storage system incorporates permanently empty blocks into each stripe, distributed among all the data storage devices, to accelerate rebuild time by reducing the number of blocks that need to be rebuilt in the event of a failure.

Abstract: The disclosure is directed to a system and method of generating soft-orthogonal syncmarks for at least a first set of tracks and a second set of tracks. Random pairs of sync patterns are searched to identify one or more pairs where the sync patterns of each pair exhibit delta-like autocorrelation and small cross-correlation with each other and with preamble portions of the tracks. Then a pair of sync patterns is selected from the one or more identified pairs, where the selected pair includes sync patterns that are distinguishable from the user data portions of the tracks at least partially based upon a data characteristic of the user data portions of the tracks. The selected pair of sync patterns is then used to generate a first syncmark for the first set of tracks and a second syncmark for the second set of tracks.

Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.

Abstract: An apparatus for controlling network traffic is provided. The apparatus includes: a data object service providing module generating a data check service frame; a message service providing module generating a data transmission service frame; a frame delay module adjusting a generation period of the data check service frame generated by the data object service providing module; a traffic analysis module comparing a data transmission amount of the data transmission service frame generated by the message service providing module with a reference data transmission amount, wherein the traffic analysis module determines a generation period of the data check service frame according to a comparison result, and controls the operation of the frame delay module according to a determined generation period; and a transmit queue transmitting a service frame transmitted from the traffic analysis module to a control area network open (CANopen) network.

Abstract: The present disclosure relates to an inverter with power cell of dual structure for use in high input voltage by changing a conventional 6-level cascaded H-bridge multilevel inverter to thereby reduce product development cost, manufacturing cost and volume of the product, the inverter including a first SMPS (Switching Mode Power Supply) connected to a first power cell region, a second SMPS connected to a second power cell region and a controller connecting the first and second SMPSs, where each phase is formed by serially connecting a plurality of power cells formed with a plurality of stages operated by receiving a power supplied from a phase shift transformer, and each of the plurality of power cells is mutually connected, and includes the first power cell region and the second power cell region independently operating.

Abstract: A power factor corrector correcting the power factor of an alternating current (AC) voltage is disclosed. A power factor correcting unit corrects the power factor of the AC voltage. A smoothing unit smoothes a power factor corrected voltage and includes a film condenser and a plurality of electrolytic condensers. A rectified voltage is applied to one end of an inductor. One end of a switch is connected to the other end of the inductor, and the other end of the switch is earthed. One end of a diode is connected to one end of the switch. One end of a film condenser is connected to the other end of the diode, and the other end of the film condenser is earthed. An electrolytic condenser is parallel-connected to the film condenser.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.

Abstract: The present invention is related to systems and methods for branch metric calculation based on multiple data streams in a data processing circuit.

Abstract: Disclosed is a method for measuring opening and closing delay time of elevator brake, the method including outputting, by a brake signal output unit, a brake signal, receiving, by a brake signal checking unit, the brake signal and determining whether the brake signal is an opening signal or a closing signal to output an opening/closing determination signal, receiving, by a brake counter unit, the opening/closing determination signal, and starting a count for measuring a brake opening time or a brake closing time to accumulate and output counted value, determining, by a motor drive checking unit, whether a motor configured to drive an elevator is driven upon receipt of the counted values and outputting a drive determination signal, and receiving, by a brake opening/closing delay computation unit, the drive determination signal and the counted value to compute a brake opening/closing delay time.

Abstract: Provided is a power factor correction circuit correcting a power factor of AC voltage. The power factor correction circuit includes: a rectifying unit stopping rectifying the AC voltage in a transient state and generating an rectified voltage by rectifying the AC voltage in a steady state; a power factor correction unit generating a power-factor-corrected voltage by correcting the rectified voltage; a smoothing unit generating a smoothed voltage by smoothing the power-factor-corrected voltage; and an inrush current limiting unit providing a limited current by limiting an inrush current generated by the AC voltage in the transient state and stopping providing a current to the smoothing unit.

Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate when decoding values encoded at a higher code rate.

Abstract: A gate driver is provided. The gate driver amplifies an input control signal to drive gates of high and low side transistors. A high side driving chip amplifies a high side control signal for controlling the high side transistor and outputs the amplified high side control signal to the gate of the high side transistor. A low side driving chip amplifies a low side control signal and outputs the amplified low side control signal to the gate of the low side transistor. An emitter terminal of the gate of the high side transistor is connected to a collector terminal of the low side transistor. The high side driving chip is separately prepared from the low side driving chip.

Abstract: Systems and methods presented herein provide for input/output shipping between storage controllers in a storage system. One storage system comprises a plurality of logical volumes, a host driver operable to process input/output requests to the logical volumes, and a plurality of storage controllers coupled between the server and the logical volumes. A first of storage controllers is operable to receive an input/output request from the host driver for one of the logical volumes, and transfer a command to a second of the storage controllers to retrieve the data of the input/output request. The second storage controller processes the command from the first storage controller, and retrieves the data associated with the input/output request.

Abstract: A method of detecting the states of power cables in an inverter system supplying power generated from an inverter to a motor by using three phase power cables is provided. The method includes: calculating the location of a current space vector for a first period when the first period arrives; using the calculated location of the current space vector for the first period to calculate the predicted location of the current space vector for a second period; calculating the actual location of the current space vector for the second period when the second period arrives; comparing the calculated predicted location with the actual location; and detecting the states of the three phase power cables according to a comparison result.

Abstract: This invention relates to a photovoltaic inverter, capable of connecting a plurality of photovoltaic modules to each input port of a multi-string photovoltaic inverter through a single booster. The photovoltaic inverter disclosed herein includes a plurality of input portions connected in series to a plurality of photovoltaic modules, respectively, a plurality of reactors connected in series to the plurality of input portions, respectively, a first capacitor configured to charge DC voltages of the plurality of photovoltaic modules, respectively, transferred through the plurality of input portions, a first resistor connected in parallel to the first capacitor, a booster unit connected in parallel to the first capacitor and m the first resistor connected in parallel to each other, and configured to boost the voltages charged in the first capacitor, and an inverter unit configured to convert the voltage boosted by the booster unit into an AC voltage to provide to a grid.

Abstract: An apparatus for cooling inverter is disclosed, whereby an optimum heat radiation effect can be accomplished, because a flow part is divided in response to heat generation amount of an electric element arranged inside a housing to adjust an air flow.

Abstract: An apparatus having a plurality of first circuits, a second circuit and a plurality of processor circuits is disclosed. Each first circuit is configured to store a plurality of samples corresponding to a plurality of channels. At least two of the samples having different widths. The second circuit is configured to store a plurality of frames each sized to contain two or more of the samples. The processor circuits are configured to (i) read the samples from the first circuits respectively, (ii) generate a transmit one of the frames by writing the samples to the second circuit based on one or more access pointers and (iii) pass control of the access pointers among the processor circuits.

Abstract: Provided is a temperature measurement apparatus using a negative temperature coefficient (NTC) thermistor. A temperature sensor includes the NTC thermistor and a variable resistor part. A resistance value of the variable resistor part varies between a default resistance value for measuring a temperature and a temporary resistance value for determining a disconnection. An abnormal operation determination unit determines whether the NTC thermistor is disconnected, based on an output voltage of the temperature sensor when the variable resistor part has the temporary resistance value.